My Inquiry
My Account
Nexperia USA Inc. 74AUP1G34GW,125
.jpg)
- Part No.:
- 74AUP1G34GW,125
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 5-TSSOP, SC-70-5, SOT-353
- Datasheet:
-
74AUP1G34GW,125.pdf
- Description:
- IC BUF NON-INVERT 3.6V 5TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:5,544
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
74AUP1G34GW,125 from Nexperia is a single low-power CMOS buffer with Schmitt-trigger input, designed for signal conditioning and noise-immune level translation in ultra-low-voltage systems. It operates across 0.8 V to 3.6 V supply, delivers ≤1.4 μA max ICC at 125 °C, supports IOFF partial power-down, and is qualified from −40 °C to +125 °C in TSSOP5 (SOT353-1) package. It enables robust interfacing in battery-powered IoT sensor nodes.
For engineers reviewing the 74AUP1G34GW,125 datasheet, 74AUP1G34GW,125 pinout, 74AUP1G34GW,125 application, or 74AUP1G34GW,125 equivalent, key selection criteria include its sub-1-μA static current at 125 °C, Schmitt-trigger hysteresis (≥0.1×VCC), IOFF leakage <±0.75 μA during power-down, propagation delay as low as 1.0 ns at 3.0 V/CL=5 pF, and guaranteed operation down to 0.8 V.
Technical Context
This device implements a non-inverting buffer with hysteresis on the input stage, enabling reliable switching in presence of slow-rising or noisy signals. Its IOFF circuit actively disables output terminals when VCC = 0 V, preventing backflow current and supporting hot-insertion in multi-rail systems.
The AUP logic family uses optimized transistor sizing to achieve ultra-low dynamic power (CPD = 4.0 pF at 3.6 V) while maintaining rail-to-rail output swing and high noise immunity (VIH ≥ 2.0 V / VIL ≤ 0.9 V at VCC = 3.6 V). It complies with JEDEC standards JESD8-12 through JESD8C across five voltage bands.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 0.8 V to 3.6 V - Enables direct interface with 0.9 V logic, 1.2 V cores, 1.8 V I/O, and 3.3 V peripherals without level shifters. |
| Max ICC (Tamb = 125 °C) | 1.4 μA - Ensures <1.5 μW static power at 1.8 V, critical for multi-year battery life in always-on sensors. |
| IOFF Leakage (VCC = 0 V) | ±0.75 μA - Limits backfeed current during system sleep, protecting powered-down domains in mixed-supply SoC interfaces. |
| tpd (VCC = 3.0 V, CL = 5 pF) | 1.0 ns (max) - Supports >500 MHz data rates in short-reach signal routing (e.g., MCU GPIO expansion). |
| VIL / VIH (VCC = 3.6 V) | 0.9 V / 2.0 V - Provides 1.1 V hysteresis margin, rejecting EMI spikes up to ±500 mV on PCB traces. |
| Operating Temperature | −40 °C to +125 °C - Validated for under-hood automotive modules, industrial motor controllers, and outdoor edge devices. |
| ESD Robustness | HBM >5000 V, CDM >1000 V - Survives handling and board-level transients without external protection diodes. |
Pinout & Package
TSSOP5 (SOT353-1) package: plastic thin shrink small outline, 5-lead, 1.25 mm body width, 0.65 mm lead pitch, 1.1 mm height. Pin 1 index located at lower-left corner below marking code 'aN'.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | n.c. | No internal connection - left floating; no PCB trace required; improves thermal isolation and reduces parasitic coupling. |
| 2 | A | Data input - accepts Schmitt-triggered signals; hysteresis ensures clean transitions even with rise/fall times up to 200 ns/V. |
| 3 | GND | Ground reference - must be low-impedance; decoupling capacitor (100 nF) placed within 2 mm for stable 1.2 V operation. |
| 4 | Y | Non-inverting buffered output - drives capacitive loads ≤30 pF with <4.2 ns max tpd at 3.6 V; supports fan-out of 10+ AUP gates. |
| 5 | VCC | Supply voltage - powers both input and output stages; IOFF activates automatically when VCC drops below 0.2 V. |
Key Features
| Feature | Design Value |
|---|---|
| Schmitt-trigger input | Hysteresis ≥0.1×VCC ensures noise rejection on long PCB traces or unshielded cables in industrial sensor hubs. |
| IOFF partial power-down | Output disabled at VCC = 0 V; prevents back-current into powered subsystems during firmware updates or sleep mode. |
| Ultra-low ICC | ≤0.9 μA typical at 25 °C and 0.8 V - extends coin-cell lifetime beyond 10 years in wake-on-event applications. |
| Overvoltage-tolerant inputs | Accepts up to 3.6 V regardless of VCC setting - allows safe interfacing with higher-voltage legacy peripherals. |
| JEDEC-compliant voltage bands | Fully specified per JESD8-12 (0.8–1.3 V), JESD8-11 (0.9–1.65 V), etc. - guarantees timing and logic behavior across all target rails. |
Applications
| Industrial Sensor Interface | Low-Power Wearable Controller |
|---|---|
|
Use Scenario: Signal conditioning between MEMS accelerometer (1.2 V analog domain) and 0.9 V MCU GPIO. IC Role / Device Role / Timing Role: Single-buffer isolates noise-sensitive analog section from digital switching noise; Schmitt trigger cleans slow ramp outputs from RC-filtered sensor lines. Use Value: Eliminates need for discrete RC+hysteresis circuit, reducing BOM count by 3 components and saving 1.2 mm² PCB area. |
Use Scenario: Level-shifting and debouncing push-button inputs in a Bluetooth LE hearable with 1.1 V core voltage. IC Role / Device Role / Timing Role: Input buffer provides hysteresis to suppress mechanical switch bounce; IOFF prevents current leakage when main SoC is powered off. Use Value: Enables true zero-power button monitoring - system draws only 0.75 μA during standby, meeting 365-day battery life target. |
| Automotive Body Control Module | Smart Home Hub I/O Expansion |
|
Use Scenario: Interfacing LIN transceiver (5 V tolerant) with 1.8 V microcontroller in door module. IC Role / Device Role / Timing Role: Buffer translates 5 V logic edges to 1.8 V domain while suppressing ESD-induced glitches via built-in 5 kV HBM protection. Use Value: Replaces dual discrete MOSFET level shifter + TVS array, cutting assembly cost by $0.08/unit and improving EMC test margin by 4 dB. |
Use Scenario: Driving multiple LED indicators and optocoupler inputs from a 3.3 V ESP32-WROOM-32 GPIO bank. IC Role / Device Role / Timing Role: Output buffer provides 4 mA drive strength at 3.3 V while limiting overshoot to <10 % of VCC for clean LED turn-on. Use Value: Prevents false triggering of downstream optocouplers due to ringing; eliminates need for series damping resistors. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G34DBVR | Higher ICC (10 μA typ), no Schmitt input, 1.65–5.5 V range | Lacks hysteresis; unsuitable for slow/noisy inputs; requires external pull-up for open-drain compatibility | Select only if VCC ≥ 1.65 V and input edges are fast/clean; avoid in battery-critical or EMI-prone environments. |
| 74LVC1G17GW,125 | Same package, identical Schmitt input, but higher ICC (2.5 μA max at 125 °C) | Valid for same use cases but consumes ~2× more static power - impacts battery life in always-on nodes | Prefer 74AUP1G34GW,125 where sub-1.5 μA ICC is mandatory; use LVC1G17 only if AUP stock is constrained. |
Compared with SN74LVC1G34DBVR and 74LVC1G17GW,125, the 74AUP1G34GW,125 uniquely combines Schmitt-trigger input, 0.8 V operation, and <1.5 μA ICC at 125 °C - making it the sole choice for ultra-low-power, noise-immune buffering in energy-harvesting and coin-cell designs.
Availability
74AUP1G34GW,125 is available at Aetrix Electronics and suitable for industrial sensor nodes, automotive body electronics, and portable medical devices requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74AUP1G34GW,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions for automotive, industrial, and mobile markets.
The 74AUP (Advanced Ultra-low Power) logic family targets ultra-low-voltage, ultra-low-power applications - specifically engineered for battery-operated and energy-constrained systems where sub-microamp static current and wide-VCC flexibility are mandatory.
FAQ
Does 74AUP1G34GW,125 support true bidirectional operation?
No. It is a unidirectional non-inverting buffer with fixed input (pin 2) and output (pin 4). The device lacks enable control or bus-hold functionality, and its IOFF feature only disables the output driver - it does not configure pins as high-impedance bidirectional I/O. For bidirectional translation, a dedicated bus switch or dual-supply level shifter is required.
Can 74AUP1G34GW,125 be used with VCC = 0 V while input A is driven at 3.3 V?
Yes. Inputs are overvoltage tolerant up to 3.6 V independent of VCC. With VCC = 0 V, the IOFF circuit disables the output (pin 4), and input leakage remains ≤±0.75 μA. This allows safe "hot insertion" into live backplanes or debugging interfaces where the host system remains powered while the buffer's supply is off.
What is the minimum load capacitance this buffer can drive without oscillation?
The device is characterized down to CL = 0 pF and exhibits no instability with purely resistive or open-circuit loads. Its output stage is designed for capacitive loading up to 30 pF (per datasheet Table 8), and it remains stable with 0 pF - making it suitable for driving high-impedance scope probes, ADC sample-and-hold inputs, or unterminated transmission lines in low-speed debug links.
Is the Schmitt-trigger hysteresis voltage fixed or VCC-dependent?
Hysteresis is VCC-dependent: typical hysteresis = 0.1 × VCC (minimum 0.1×VCC across −40 °C to +125 °C). At VCC = 1.2 V, VIH − VIL ≈ 120 mV; at VCC = 3.3 V, it is ≈ 330 mV. This scaling ensures consistent noise margin across the full operating range without requiring external resistor networks.
74AUP1G34GW,125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AUP
- Package/Case:
- 5-TSSOP, SC-70-5, SOT-353
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- Push-Pull
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 5-TSSOP
74AUP1G34GW,125 FAQ
1.How can I place an order for 74AUP1G34GW,125 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP1G34GW,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP1G34GW,125 reliable?
The price and inventory of 74AUP1G34GW,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1G34GW,125 is usually 5 days.
3.What payment methods are accepted for 74AUP1G34GW,125?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP1G34GW,125 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74AUP1G34GW,125?
74AUP1G34GW,125 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP1G34GW,125 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP1G34GW,125?
For technical support, including 74AUP1G34GW,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1G34GW,125 requirements.
6.How does Aetrix verify that 74AUP1G34GW,125 is sourced from the original manufacturer or authorized distributors?
All 74AUP1G34GW,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1G34GW,125 meets industry standards.
7.What is the process for return or replacement of 74AUP1G34GW,125?
All 74AUP1G34GW,125 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1G34GW,125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP1G34GW,125 part is unused and in its original packaging.
Return procedure for 74AUP1G34GW,125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74AUP1G34GW,125 Tags
-
SN74LVC1G17DBVR
Texas Instruments
-
SN74LVC1G07DCKR
Texas Instruments
-
SN74LVC1G17DCKR
Texas Instruments
-
SN74LVC1G07DBVR
Texas Instruments
-
SN74LVC1G125DCKR
Texas Instruments
-
SN74AHCT1G126DBVR
Texas Instruments
-
SN74LVC1G125DBVR
Texas Instruments
-
SN74AHCT1G125DBVR
Texas Instruments
-
SN74LVC2G17DBVR
Texas Instruments
-
SN74LVC2G07DCKR
Texas Instruments
-
SN74LVC1G34DCKR
Texas Instruments
-
SN74LVC2G17DCKR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
