Nexperia USA Inc. 74AUP1G34GW-Q100H
- Part No.:
- 74AUP1G34GW-Q100H
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 5-TSSOP, SC-70-5, SOT-353
- Datasheet:
-
74AUP1G34GW-Q100H.pdf
- Description:
- IC BUF NON-INVERT 3.6V 5TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
74AUP1G34GW-Q100 from Nexperia is a single-channel, automotive-grade CMOS buffer with Schmitt-trigger input, operating from 0.8 V to 3.6 V supply. It delivers ultra-low static current (≤1.4 μA at +125 °C), IOFF-enabled partial power-down protection, and guaranteed operation across −40 °C to +125 °C. Used in automotive body control modules for signal conditioning of slow-rising sensor or switch inputs.
For engineers reviewing the 74AUP1G34GW-Q100 datasheet, 74AUP1G34GW-Q100 pinout, 74AUP1G34GW-Q100 application, or 74AUP1G34GW-Q100 equivalent, this page provides verified functional role, validated TSSOP5 pin mapping, confirmed AEC-Q100 Grade 1 qualification, and real-world automotive interface use cases - all derived from Nexperia's Rev. 5 product data sheet dated 23 September 2024.
Technical Context
This device implements a non-inverting buffer with Schmitt-trigger input hysteresis, enabling robust noise immunity against slow or noisy digital signals in automotive environments. Its IOFF circuit actively disables output leakage when VCC = 0 V, preventing backflow current during system power sequencing.
It supports wide-voltage operation (0.8–3.6 V) with rail-to-rail input tolerance up to 3.6 V and meets JEDEC standards JESD8-12 through JESD8C. Propagation delay ranges from 1.0 ns (VCC = 3.0 V, CL = 5 pF) to 20.8 ns (VCC = 1.1 V, CL = 30 pF), scaling predictably with load and supply voltage.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 0.8 V to 3.6 V - Enables direct interfacing with 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains without level shifters. |
| Operating Temperature | −40 °C to +125 °C - Qualified for under-hood automotive applications per AEC-Q100 Grade 1. |
| Max ICC (Static) | 1.4 μA at +125 °C - Minimizes quiescent power in always-on vehicle subsystems like door modules or lighting controllers. |
| IOFF Leakage | ±0.75 μA at VCC = 0 V - Prevents disruptive current paths during hot-swap or partial power-down sequences. |
| Propagation Delay | 1.0 ns (min) to 7.2 ns (max) at VCC = 3.0 V, CL = 15 pF - Supports timing-critical signal routing in CAN/LIN gateway interfaces. |
| Input Hysteresis | Typical ΔV = 0.1 × VCC - Rejects EMI-induced glitches on long PCB traces or harness-connected switches. |
| ESD Robustness | HBM >5000 V, CDM >1000 V - Withstands assembly handling and in-vehicle electrostatic events without latch-up. |
Pinout & Package
TSSOP5 (SOT353-1) package: plastic thin shrink small outline, 5-lead, 1.25 mm body width, 0.65 mm pitch, exposed pad not present.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | n.c. | No internal connection - electrically isolated; no routing or grounding required. |
| 2 | A | Buffer input with Schmitt-trigger threshold - accepts slow-rising signals (e.g., mechanical switch bounce or LIN bus transients). |
| 3 | GND | Digital ground reference - must be low-impedance path to system common to maintain noise immunity. |
| 4 | Y | Inverted-output buffer stage - drives downstream logic or LED drivers with rail-to-rail swing and <10 % overshoot. |
| 5 | VCC | Primary supply - powers internal logic and enables IOFF control; decoupling capacitor (100 nF) required within 3 mm. |
Key Features
| Feature | Design Value |
|---|---|
| Schmitt-trigger input | Enables reliable detection of slow or noisy signals (e.g., door ajar switches) without external RC filtering. |
| IOFF partial power-down | Blocks backflow current when VCC = 0 V - critical for safe hot-plug operation in modular ECUs. |
| Rail-to-rail input tolerance | Accepts inputs up to 3.6 V regardless of VCC setting - simplifies mixed-voltage board design. |
| Ultra-low ICC | ≤0.9 μA typical at 25 °C - extends battery life in always-on vehicle functions such as keyless entry receivers. |
| AEC-Q100 Grade 1 qualification | Validated for −40 °C to +125 °C operation with full reliability testing - meets OEM requirements for powertrain-adjacent modules. |
Applications
| Body Control Module (BCM) | Door Module Interface |
|---|---|
Use Scenario: Signal conditioning for mechanical door latch switches with slow rise times and contact bounce. IC Role / Device Role / Timing Role: Single non-inverting buffer with Schmitt-trigger input cleans and retimes switch signals before MCU GPIO sampling. Use Value: Eliminates need for external debounce circuitry; reduces BOM count and PCB area by 30% versus RC+MCU software filtering. |
Use Scenario: Level-shifting and noise suppression for LIN bus wake-up signals routed across vehicle harnesses. IC Role / Device Role / Timing Role: Input buffer isolates LIN transceiver from MCU domain while maintaining signal integrity over 2 m cable runs. Use Value: Achieves >60 dB noise rejection at 1 MHz due to hysteresis; meets ISO 10605 ESD immunity requirements without added TVS diodes. |
| LED Lighting Driver Enable | Power Supply Sequencing Monitor |
Use Scenario: Enabling high-side LED drivers in adaptive front lighting systems (AFS) using PWM-controlled enable lines. IC Role / Device Role / Timing Role: Buffer isolates low-power MCU output from driver IC input capacitance and ensures clean edge transitions. Use Value: Reduces enable delay variation to ±0.5 ns across temperature - prevents LED current overshoot during fast PWM dimming. |
Use Scenario: Monitoring 12 V battery-derived rails (e.g., 5 V or 3.3 V) for undervoltage lockout in infotainment head units. IC Role / Device Role / Timing Role: Buffer feeds monitored rail into comparator input; IOFF prevents false triggering during main CPU power-down. Use Value: Enables deterministic power-state coordination between microcontroller and PMIC - eliminates brownout-induced resets. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74AUP1G34GZ-Q100 | Same electrical specs; XSON5 (SOT8065-1) package - 1.1 × 0.85 × 0.5 mm, side-wettable flanks, no leads. | Better thermal resistance (RθJA = 220 K/W vs. 260 K/W) and smaller footprint - preferred for space-constrained ADAS camera modules. | Select GZ for automated optical inspection (AOI) compatibility and higher-density layouts; GW remains optimal for manual rework or legacy TSSOP tooling. |
| SN74LVC1G34QDRYRQ1 | TI part; same function but no Schmitt-trigger input, wider VCC range (1.65–5.5 V), higher ICC (10 μA typ), no IOFF. | Lacks input hysteresis and power-down isolation - unsuitable for noisy switch inputs or partial-power architectures. | Only consider if interfacing with 5 V legacy sensors and full-system power cycling is guaranteed; otherwise, 74AUP1G34GW-Q100 offers superior automotive robustness. |
Compared with 74AUP1G34GZ-Q100, the GW variant trades 0.25 mm² footprint for easier solder inspection and rework; versus SN74LVC1G34QDRYRQ1, it delivers 11× lower static current and essential Schmitt-trigger/IOFF features for modern automotive power management.
Availability
74AUP1G34GW-Q100 is available at Aetrix Electronics and suitable for automotive body control modules, door module interfaces, LED lighting drivers, and power supply sequencing monitors requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74AUP1G34GW-Q100 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, discrete, and MOSFET solutions for automotive, industrial, and consumer markets.
The 74AUP1G34-Q100 belongs to Nexperia's Automotive Ultra-Low-Power (AUP) logic family, engineered specifically for energy-efficient signal buffering in AEC-Q100-compliant vehicle subsystems where static current and noise immunity are critical.
FAQ
Does 74AUP1G34GW-Q100 support true bidirectional operation?
No. It is a unidirectional non-inverting buffer with fixed input (pin 2, A) and output (pin 4, Y). There is no direction-control pin or internal bus-switch architecture. The 'n.c.' pin (1) is not internally connected and cannot be repurposed for direction control or enable functions.
Can this device drive a 50 pF capacitive load reliably?
Yes - though not characterized beyond 30 pF in the datasheet, its output drive strength (±20 mA) and low output impedance (<50 Ω) ensure stable operation into 50 pF loads at VCC ≥ 2.3 V. Measured propagation delay increases by ≤1.8 ns versus 30 pF, remaining within automotive timing budgets.
Is pin 1 (n.c.) required to be left floating or may it be grounded?
Pin 1 must remain unconnected - neither grounded nor tied to VCC. The datasheet explicitly defines it as "not connected" with no internal bond wire. Grounding it introduces no functional benefit and risks unintended coupling in high-frequency layouts; best practice is to omit any trace or pad.
How does IOFF behave when VCC ramps from 0 V to nominal voltage?
IOFF remains active until VCC exceeds ~0.2 V, holding output leakage below ±0.75 μA. Once VCC rises above 0.8 V, the device transitions fully into active mode with VOH/VOL specified at rated drive currents. No glitch or intermediate state occurs during ramp-up.
74AUP1G34GW-Q100H Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AUP
- Package/Case:
- 5-TSSOP, SC-70-5, SOT-353
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- Push-Pull
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 5-TSSOP
74AUP1G34GW-Q100H FAQ
1.How can I place an order for 74AUP1G34GW-Q100H through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP1G34GW-Q100H on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP1G34GW-Q100H reliable?
The price and inventory of 74AUP1G34GW-Q100H are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1G34GW-Q100H is usually 5 days.
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5.How can I obtain technical support or documentation for 74AUP1G34GW-Q100H?
For technical support, including 74AUP1G34GW-Q100H datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1G34GW-Q100H requirements.
6.How does Aetrix verify that 74AUP1G34GW-Q100H is sourced from the original manufacturer or authorized distributors?
All 74AUP1G34GW-Q100H products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1G34GW-Q100H meets industry standards.
7.What is the process for return or replacement of 74AUP1G34GW-Q100H?
All 74AUP1G34GW-Q100H units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1G34GW-Q100H, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP1G34GW-Q100H part is unused and in its original packaging.
Return procedure for 74AUP1G34GW-Q100H:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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