Nexperia USA Inc. 74AUP1G34UKAZ

Overview

74AUP1G34UKAZ from Nexperia is a single low-power CMOS buffer with Schmitt-trigger input, designed for signal conditioning in ultra-low-voltage digital systems. It operates across 0.8 V to 3.6 V supply, delivers <1.4 μA max ICC at 125 °C, supports IOFF partial power-down, and features overvoltage-tolerant inputs up to 3.6 V - enabling robust interfacing between mixed-voltage domains in portable sensor nodes and battery-powered IoT edge devices.

For engineers reviewing the 74AUP1G34UKAZ datasheet, 74AUP1G34UKAZ pinout, 74AUP1G34UKAZ application, or 74AUP1G34UKAZ equivalent, this page provides verified functional identity, validated pin mapping for SOT8065-1 (XSON5), confirmed Schmitt-trigger noise immunity specs, and real-world use cases in voltage-level translation and bus driving where static current and power-down isolation are critical.

Technical Context

The 74AUP1G34UKAZ implements a non-inverting buffer with hysteresis on the A input, enabling reliable operation with slow-rising or noisy signals. Its IOFF circuit actively disables output leakage when VCC = 0 V, limiting backflow current to ±0.75 μA - essential for hot-swap and multi-rail system partitioning.

Propagation delay ranges from 1.4 ns (VCC = 3.6 V, CL = 5 pF) to 7.2 ns (VCC = 0.8 V, CL = 30 pF), while input and output capacitances remain tightly controlled at CI = 0.8 pF and CO = 1.7 pF - supporting high-speed signal integrity in space-constrained PCB layouts with minimal loading.

Key Specifications

Pinout & Package

XSON5 package (SOT8065-1): plastic thermal-enhanced extremely thin small outline with side-wettable flanks (SWF); 5 terminals; body size 1.1 × 0.85 × 0.5 mm; compatible with automated optical inspection (AOI) and reflow soldering.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar buffer applications.

Compared with SN74LVC1G17DBVR and 74LVC1G34GW, the 74AUP1G34UKAZ uniquely combines sub-μA static current, Schmitt-trigger noise rejection, and IOFF isolation - making it the sole option for battery-critical, mixed-rail, and EMI-prone embedded signal routing.

Availability

74AUP1G34UKAZ is available at Aetrix Electronics and suitable for industrial sensor interfaces, portable medical devices, automotive body control modules, and smart home hubs requiring stable component supply across extended temperature and ultra-low-power constraints.

Supply support for 74AUP1G34UKAZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, discrete, and MOSFET solutions for automotive, industrial, and consumer markets.

The 74AUP (Advanced Ultra-low Power) logic family targets energy-constrained applications demanding nanowatt standby, wide VCC scalability, and robust IO behavior - specifically engineered for battery-powered IoT endpoints and automotive domain controllers.

FAQ

What is the maximum allowable input voltage when VCC = 0 V?

The 74AUP1G34UKAZ supports input voltages up to +4.6 V regardless of VCC state, per Absolute Maximum Ratings (Table 5). This allows safe connection to active upstream signals during host power-down, with IOFF limiting back-current to ±0.75 μA - eliminating need for external blocking diodes.

Does the Schmitt-trigger input affect propagation delay symmetry?

No - tPLH and tPHL are identical (both labeled tpd in Table 8) because the Schmitt action applies only to input threshold detection, not output stage timing. Measured delays remain symmetric across rising/falling edges, with typical tpd = 1.4 ns at 3.6 V/5 pF.

Can the n.c. pin on SOT8065-1 be used as a thermal pad or grounded?

No - the n.c. terminal is internally unconnected and must remain floating. It is not bonded to die substrate or thermal slug. Grounding or biasing it may cause unpredictable leakage or latch-up; Nexperia's package drawings (Fig. 12) explicitly define it as "not connected" with no internal metal path.

How does IOFF behave when VCC ramps from 0 V to nominal?

IOFF remains active until VCC exceeds ~0.2 V, then transitions smoothly to normal operation. ΔIOFF (Table 7) specifies ≤ ±0.75 μA leakage across VCC = 0–0.2 V, ensuring no disruptive current injection into downstream circuits during power-up sequencing.