NXP Semiconductors 74AUP1G386GM,115

Overview

74AUP1G386GM,115 from NXP Semiconductors is a single 3-input XOR gate in ultra-low-power CMOS technology, operating from 0.8 V to 3.6 V supply, with typical propagation delay of 3.0 ns at V_CC = 3.3 V and 25 °C, and maximum I_CC of 0.9 µA at V_CC = 3.3 V. It serves as a logic-level combinatorial function block in battery-powered sensor interfaces and portable IoT node control paths.

For engineers reviewing the 74AUP1G386GM,115 datasheet, 74AUP1G386GM,115 pinout, 74AUP1G386GM,115 application, or 74AUP1G386GM,115 equivalent, key selection criteria include supply voltage range compatibility, static current draw in deep-sleep states, propagation delay under low-V_CC, and guaranteed logic threshold behavior across temperature.

Technical Context

This device implements standard Boolean XOR logic (Y = A ⊕ B ⊕ C) using silicon-proven AUP (Advanced Ultra-low Power) process technology. Its input thresholds are referenced to V_CC, enabling robust operation across the full 0.8–3.6 V range without external level-shifting.

It features overvoltage-tolerant inputs up to 3.6 V regardless of supply voltage, and outputs drive ±4 mA at V_CC = 3.0 V. The design includes ESD protection exceeding 2-kV HBM per JESD22-A114.

Key Specifications

Pinout & Package

Supplied in a 6-pin XSON6 (1.45 × 1.0 mm, 0.5 mm pitch) package with wettable flank profile for automated optical inspection.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 3-input XOR logic applications.

Compared with SN74LVC1G386DBVR and 74AHC1G386GW,125, the 74AUP1G386GM,115 uniquely balances sub-µA quiescent current with 3.0 ns delay across 0.8–3.6 V, making it optimal for battery-constrained, multi-rail IoT endpoints where both energy and timing matter.

Availability

74AUP1G386GM,115 is available at Aetrix Electronics and suitable for wireless sensor nodes, portable medical monitors, and industrial asset trackers requiring stable component supply and long-term lifecycle assurance.

Supply support for 74AUP1G386GM,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.

The 74AUP logic family targets ultra-low-power, wide-supply-range digital functions for battery-operated and energy-harvesting applications, emphasizing static current minimization without sacrificing timing predictability.

FAQ

What is the minimum supply voltage at which 74AUP1G386GM,115 guarantees correct logic operation?

The device is fully specified down to 0.8 V V_CC, with guaranteed high/low output levels, input thresholds, and propagation delay across –40 °C to +125 °C. At 0.8 V, t_PD increases to 12.5 ns max, and output drive reduces to ±1.5 mA, but logical correctness is maintained per datasheet AC/DC specs.

Can 74AUP1G386GM,115 inputs be driven by 5 V signals?

No. Inputs are overvoltage-tolerant only up to 3.6 V, regardless of V_CC. Driving with 5 V violates absolute maximum ratings and risks permanent damage. For 5 V interface, use a discrete resistor divider or a dedicated level translator such as NXP NX3V01.

Is there a version of this XOR gate with Schmitt-trigger inputs?

No. The 74AUP1G386GM,115 does not include Schmitt-trigger inputs. NXP offers the 74AUP1G57 (universal configurable gate) and 74AUP1G17 (Schmitt-trigger buffer) as alternatives when hysteresis is required, but neither provides 3-input XOR functionality with hysteresis.

Does this device support partial power-down or I/O isolation when V_CC is unpowered?

No. The 74AUP1G386GM,115 lacks I/O protection during V_CC = 0 V. Inputs and outputs must remain within –0.5 V to V_CC + 0.5 V at all times. For hot-swap or partial-power-down scenarios, add series resistors or use a bus-hold or I²C-compatible logic family with power-off protection.