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Nexperia USA Inc. 74AUP1G386GW,125
- Part No.:
- 74AUP1G386GW,125
- Manufacturer:
- Nexperia USA Inc.
- Category:
- Gates and Inverters
- Package:
- 6-TSSOP, SC-88, SOT-363
- Datasheet:
-
74AUP1G386GW,125.pdf
- Description:
- IC GATE XOR 1CH 3-INP 6TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:1,775
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Product details
Overview
74AUP1G386GW,125 from Nexperia is a single 3-input EXCLUSIVE-OR gate with Schmitt-trigger inputs, operating across 0.8 V to 3.6 V supply, delivering ultra-low static current (≤0.9 μA max), IOFF-enabled partial power-down protection, and propagation delay as low as 1.0 ns at 3.0 V/CL=5 pF. It serves in voltage-level agnostic logic interfacing, battery-powered sensor signal conditioning, and noise-prone industrial control I/O conditioning.
For engineers reviewing the 74AUP1G386GW,125 datasheet, 74AUP1G386GW,125 pinout, 74AUP1G386GW,125 application, or 74AUP1G386GW,125 equivalent, this device supports low-voltage mixed-signal system integration where input rise/fall time tolerance, sub-1-μA quiescent current, and guaranteed IOFF behavior during power sequencing are critical selection criteria.
Technical Context
The 74AUP1G386GW,125 implements a true 3-input XOR Boolean function (Y = A ⊕ B ⊕ C) with Schmitt-trigger inputs that provide hysteresis (typ. 0.1 × VCC), enabling robust operation with slow or noisy signals. Its IOFF circuit actively disables outputs when VCC = 0 V, blocking backflow current up to ±0.75 μA.
It complies with JEDEC standards JESD8-12 through JESD8-B for multi-voltage operation and meets HBM ESD >5000 V and CDM >1000 V. Dynamic performance is characterized across -40 °C to +125 °C with CL-dependent tpd ranging from 1.0 ns (3.0 V, 5 pF) to 6.9 ns (3.0 V, 30 pF).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Function | 3-input exclusive-OR (Y = A ⊕ B ⊕ C); enables parity generation and controlled signal inversion |
| Supply Voltage Range | 0.8 V to 3.6 V; supports direct interface with 0.9 V, 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains |
| Max ICC (Static) | 0.9 μA at VCC = 0.8–3.6 V; enables multi-year battery life in always-on IoT endpoints |
| IOFF Leakage | ±0.75 μA at VCC = 0 V; prevents damaging back-current during hot-insertion or partial power-down |
| tpd (A/B/C → Y) | 1.0 ns min / 4.2 ns max at VCC = 3.0–3.6 V, CL = 5 pF; suitable for <100 MHz toggle-rate logic paths |
| Input Hysteresis | Typ. 0.1 × VCC; rejects noise spikes ≤100 mV on 1.0 V rails, eliminating external RC filtering |
| ESD Rating | HBM >5000 V, CDM >1000 V; withstands handling in Class 1B ESD environments without additional protection |
Pinout & Package
TSSOP6 plastic thin shrink small outline package (SOT363-2), 6-lead, body width 1.25 mm, 0.65 mm pitch, moisture sensitivity level MSL3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (A) | Data input A | Primary XOR operand; Schmitt-triggered for noise immunity and slow-edge tolerance |
| 2 (GND) | Ground reference | 0 V return path; must be low-impedance to maintain VIH/VIL thresholds and noise margin |
| 3 (B) | Data input B | Second XOR operand; electrically identical to Pin 1 with same hysteresis and voltage thresholds |
| 4 (Y) | Data output Y | Active-drive CMOS output; sinks/sourcing capability defined per VCC and load conditions |
| 5 (VCC) | Supply voltage | Power rail for internal logic; IOFF activation occurs when VCC = 0 V |
| 6 (C) | Data input C | Third XOR operand; completes 3-input parity function; fully symmetric with A and B |
Key Features
| Feature | Design Value |
|---|---|
| Wide VCC range | 0.8 V to 3.6 V enables drop-in use across legacy and next-gen low-power SoC I/O banks |
| Schmitt-trigger inputs | Input hysteresis ≥0.1 × VCC ensures reliable switching with rise/fall times up to 200 ns/V |
| IOFF partial power-down | Output high-impedance state activated at VCC = 0 V; eliminates backfeed in multi-rail systems |
| Low dynamic power | CPD = 4.4 pF at 3.3 V; enables <1 μW dynamic dissipation at 1 MHz with 5 pF load |
| High noise immunity | VIH/VIL thresholds scale with VCC (e.g., VIH = 2.0 V min at 3.0–3.6 V); maintains 70% noise margin |
Applications
| Industrial Sensor Interface | IoT Edge Node Logic |
|---|---|
|
Use Scenario: Interfacing analog sensor outputs with slow slew rates (e.g., thermistor bridges, RTD amplifiers) to microcontroller GPIOs in factory automation nodes. IC Role / Device Role / Timing Role: Signal conditioner and level translator; converts noisy, slow-rising sensor logic into clean, fast-rising MCU-compatible signals via Schmitt-trigger action. Use Value: Eliminates need for external RC filters and pull-ups, reducing BOM count by one passive per channel while maintaining timing predictability under EMI. |
Use Scenario: Implementing wake-up event arbitration in battery-powered asset trackers using multiple motion, light, and button inputs. IC Role / Device Role / Timing Role: 3-input XOR combiner feeding interrupt line; generates pulse only when odd-numbered inputs activate, enabling efficient multi-source wake detection. Use Value: Delivers sub-1-μA static current draw and IOFF isolation during sleep mode, extending coin-cell lifetime beyond 5 years. |
| Automated Test Equipment (ATE) | Medical Wearable Data Path |
|
Use Scenario: Glitch-free signal routing in modular ATE backplanes where multiple test instruments share digital control lines. IC Role / Device Role / Timing Role: Bus contention resolver; XOR of enable signals prevents simultaneous driver activation on shared data lanes. Use Value: Propagation delay variation <0.3 ns across temperature ensures deterministic timing margins in 100 MHz test clock domains. |
Use Scenario: Real-time parity checking of serial sensor data streams (e.g., SPI from ECG front-end) before transmission to BLE SoC. IC Role / Device Role / Timing Role: Hardware parity generator; computes odd/even bit count across three parallel data bits for error detection. Use Value: Operates reliably at 1.2 V core voltage with <100 ps jitter, meeting ISO 13485 functional safety timing constraints for Class IIa devices. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 3-input XOR gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G86DBVR | Higher ICC (max 10 μA), no IOFF, VCC min = 1.65 V, no Schmitt inputs | Requires clean input edges; unsuitable for partial power-down or sub-1.65 V systems | Select only if operating strictly at 1.8 V+ with fast, low-noise sources and no power sequencing requirements |
| 74LVC1G386GM,125 | Same logic, identical specs, but in XSON6 (SOT886) package - 1.0 × 1.45 × 0.5 mm, leadless | Enables higher board density and improved thermal performance in space-constrained wearables | Choose for PCB area savings and better thermal resistance (3.3 mW/K derating vs. TSSOP6's 3.7 mW/K) |
Compared with SN74LVC1G86DBVR, the 74AUP1G386GW,125 delivers 11× lower static current and Schmitt noise rejection essential for sensor interfaces; versus 74LVC1G386GM,125 it offers identical functionality in a larger but rework-friendly TSSOP6 package with established solder-reflow profiles.
Availability
74AUP1G386GW,125 is available at Aetrix Electronics and suitable for industrial sensor interfaces, IoT edge node logic, automated test equipment, and medical wearable data path applications requiring stable component supply across extended temperature ranges.
Supply support for 74AUP1G386GW,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, discrete, and MOSFET solutions, serving automotive, industrial, and consumer markets with scalable manufacturing and rigorous quality systems.
The 74AUP (Advanced Ultra-low Power) product line targets energy-constrained applications demanding sub-1-μA quiescent current, wide-VCC operation, and robust IO behavior-designed specifically for battery-powered and multi-rail embedded systems.
FAQ
Does the 74AUP1G386GW,125 support true 3-input XOR logic, and how is its truth table verified?
Yes, it implements Y = A ⊕ B ⊕ C per Table 4 in the datasheet, confirmed by functional testing across all eight input combinations at -40 °C, 25 °C, and +125 °C. The output toggles only when an odd number of inputs are HIGH, matching IEEE Std 91-1984 XOR definition for three operands.
What is the practical impact of the IOFF feature during system power-down sequences?
When VCC drops to 0 V, IOFF forces the output into high-impedance state with leakage ≤±0.75 μA, preventing back-current flow from powered downstream circuits (e.g., 3.3 V MCU GPIO) into the unpowered gate-critical for avoiding latch-up or false triggering in mixed-voltage systems.
Can the Schmitt-trigger inputs tolerate input voltages exceeding VCC, and what is the safe limit?
Inputs are overvoltage tolerant to 3.6 V regardless of VCC level (e.g., 3.3 V signal applied while VCC = 1.2 V). This is validated per datasheet Table 5 (VI max = +4.6 V absolute max, but recommended operating VI ≤ 3.6 V), enabling safe level-shifting without external clamps.
How does propagation delay vary with load capacitance, and what CL value is used for the 1.0 ns minimum spec?
tpd scales linearly with CL: at VCC = 3.0–3.6 V, tpd = 1.0 ns (min) / 4.2 ns (max) for CL = 5 pF, rising to 2.3 ns / 6.9 ns at CL = 30 pF. The 1.0 ns minimum is measured under controlled conditions (Fig. 7, CL = 5 pF, VCC = 3.0 V, Tamb = -40 °C to +125 °C).
74AUP1G386GW,125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AUP
- Package/Case:
- 6-TSSOP, SC-88, SOT-363
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- XOR (Exclusive OR)
- Number of Circuits:
- 1
- Number of Inputs:
- 3
- Features:
- -
- Voltage - Supply:
- 0.8V ~ 3.6V
- Current - Quiescent (Max):
- 500 nA
- Current - Output High, Low:
- 4mA, 4mA
- Input Logic Level - Low:
- 0.7V ~ 0.9V
- Input Logic Level - High:
- 1.6V ~ 2V
- Max Propagation Delay @ V, Max CL:
- 6.1ns @ 3.3V, 30pF
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-TSSOP
74AUP1G386GW,125 FAQ
1.How can I place an order for 74AUP1G386GW,125 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP1G386GW,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP1G386GW,125 reliable?
The price and inventory of 74AUP1G386GW,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1G386GW,125 is usually 5 days.
3.What payment methods are accepted for 74AUP1G386GW,125?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP1G386GW,125 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74AUP1G386GW,125?
74AUP1G386GW,125 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP1G386GW,125 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP1G386GW,125?
For technical support, including 74AUP1G386GW,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1G386GW,125 requirements.
6.How does Aetrix verify that 74AUP1G386GW,125 is sourced from the original manufacturer or authorized distributors?
All 74AUP1G386GW,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1G386GW,125 meets industry standards.
7.What is the process for return or replacement of 74AUP1G386GW,125?
All 74AUP1G386GW,125 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1G386GW,125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP1G386GW,125 part is unused and in its original packaging.
Return procedure for 74AUP1G386GW,125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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