Nexperia USA Inc. 74AUP1G38GM,132

Overview

74AUP1G38GM,132 from Nexperia is a single 2-input NAND gate with open-drain output, Schmitt-trigger inputs, and IOFF partial power-down capability. It operates across 0.8 V to 3.6 V supply, delivers ≤1.4 μA max ICC at −40 °C to +125 °C, supports 5 pF load propagation delay as low as 0.8 ns (VCC = 3.0–3.6 V), and features overvoltage-tolerant inputs up to 3.6 V - used in level-shifting I²C bus pull-up control and low-power sensor interface logic.

For engineers reviewing the 74AUP1G38GM,132 datasheet, 74AUP1G38GM,132 pinout, 74AUP1G38GM,132 application, or 74AUP1G38GM,132 equivalent, this device is selected for ultra-low static power, rail-to-rail input tolerance, and guaranteed operation in extended-temperature industrial systems requiring robust noise immunity and safe power sequencing.

Technical Context

This device implements a CMOS-based NAND logic function with Schmitt-trigger inputs that provide hysteresis (typ. 0.2 × VCC) to reject slow-rising or noisy signals. Its open-drain output enables wired-AND configurations and bidirectional level translation without external components.

The IOFF circuit actively disables output leakage when VCC = 0 V, limiting power-off current to ±0.75 μA while allowing inputs/outputs to be driven safely up to 3.6 V - critical for hot-swap and multi-voltage domain isolation in portable and IoT edge nodes.

Key Specifications

Pinout & Package

XSON6 plastic extremely thin small outline package (SOT886); no leads; 6 terminals; body size 1.0 mm × 1.45 mm × 0.5 mm; wettable flank design for automated optical inspection.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 2-input NAND gate applications.

Compared with SN74LVC1G38DBVR and 74LVC1G00GW,125, the 74AUP1G38GM,132 uniquely combines ultra-low ICC, Schmitt inputs, open-drain output, and IOFF in a 1.0 × 1.45 mm XSON6 package - making it the only choice for space-constrained, battery-powered systems demanding both noise resilience and safe multi-rail sequencing.

Availability

74AUP1G38GM,132 is available at Aetrix Electronics and suitable for industrial sensor interfaces, I²C level translation, low-power wake-up logic, and motor driver enable sequencing requiring stable component supply across extended temperature ranges.

Supply support for 74AUP1G38GM,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance logic, discrete, and MOSFET solutions optimized for efficiency, reliability, and miniaturization in industrial, automotive, and consumer applications.

The 74AUP (Advanced Ultra-low Power) family targets battery-operated and thermally constrained systems where sub-microamp quiescent current, wide-VCC operation, and robust signal integrity are mandatory design requirements.

FAQ

Can the 74AUP1G38GM,132 drive a 10 kΩ pull-up resistor on its open-drain output?

Yes - with VCC = 3.3 V and IO = 4 mA, VOL is guaranteed ≤0.50 V, supporting standard 10 kΩ pull-ups to 3.3 V or 5 V (via external clamp). The output can sink ≥4 mA continuously, enabling reliable I²C-standard bus driving at 400 kHz with typical rise times under 300 ns.

Does the Schmitt-trigger input affect propagation delay specifications?

Yes - the datasheet propagation delay (tpd) values include Schmitt-trigger hysteresis effects and are measured from 50% input to 50% output crossing. At VCC = 1.8 V, tpd ranges from 1.1 ns to 6.5 ns depending on load capacitance; hysteresis adds <0.3 ns deterministic delay but improves timing predictability under noise.

What is the maximum capacitive load the 74AUP1G38GM,132 can drive reliably?

The device is characterized up to 30 pF load capacitance (Table 8), with tpd increasing linearly: e.g., at VCC = 3.3 V, tpd rises from 0.8 ns (5 pF) to 2.1 ns (30 pF). For loads >30 pF, signal integrity degrades due to increased rise/fall time; add series resistance or buffer stage if CL exceeds 40 pF.

Is the n.c. pin on the SOT886 package internally bonded or floating?

Pin 5 is a true no-connect - not bonded to die, not tied to substrate, and electrically isolated. It serves mechanical stabilization and thermal dissipation; soldering it improves thermal resistance by ~5 °C/W but provides no electrical function. Do not route signals or power to this terminal.