Nexperia USA Inc. 74AUP1G57GS,132

Overview

74AUP1G57GS,132 from Nexperia is a low-power configurable multiple-function logic gate with Schmitt-trigger inputs, supporting AND, OR, NAND, NOR, XNOR, inverter, and buffer configurations via its 3-bit input control (A/B/C). It operates across 0.8 V to 3.6 V supply, delivers ≤0.9 μA max ICC at 125 °C, and features IOFF partial power-down protection. It is used in battery-powered sensor interfaces and level-shifting I/O conditioning circuits where ultra-low static power and noise immunity are critical.

For engineers reviewing the 74AUP1G57GS,132 datasheet, 74AUP1G57GS,132 pinout, 74AUP1G57GS,132 application, or 74AUP1G57GS,132 equivalent, key selection criteria include its 6-terminal XSON6 package (SOT1202), Schmitt-trigger hysteresis (≥0.53 V at 1.4 V VCC), propagation delay as low as 1.5 ns at 3.0 V/10 pF, and guaranteed operation from –40 °C to +125 °C.

Technical Context

This device implements a single configurable logic cell using CMOS technology with Schmitt-trigger inputs for robust noise rejection. Its function is determined by the logic states applied to inputs A, B, and C - no external configuration pins or registers are required. The output Y responds to all three inputs simultaneously per the defined truth table, enabling flexible re-use without hardware change.

The IOFF circuit actively disables outputs during power-down, limiting backflow current to ±0.75 μA when VCC = 0 V, making it suitable for hot-swap and partial-power-down systems. Input overvoltage tolerance up to 3.6 V allows interfacing with higher-voltage domains while powered from lower VCC rails.

Key Specifications

Pinout & Package

XSON6 plastic extremely thin small outline package (no leads); 6 terminals; body dimensions 1.0 mm × 1.0 mm × 0.35 mm (SOT1202).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar configurable logic gate applications.

Compared with 74LVC1G57GW,125, the 74AUP1G57GS,132 offers superior low-power performance and IOFF, while SN74LVC1G97DBVR matches the compact XSON6 form factor but lacks extended temperature support - making the 74AUP1G57GS,132 optimal for space-constrained, high-reliability, wide-temperature applications.

Availability

74AUP1G57GS,132 is available at Aetrix Electronics and suitable for industrial sensor interfaces, automotive body control modules, and low-power wearable electronics requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74AUP1G57GS,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions optimized for reliability and energy efficiency.

The 74AUP (Advanced Ultra-low Power) product line targets battery-powered and thermally constrained applications, emphasizing sub-μA static current, wide VCC scalability, and robust signal integrity - directly addressing design needs in IoT endpoints and automotive subsystems.

FAQ

What logic functions can the 74AUP1G57GS,132 implement?

The device implements seven logic functions - AND, OR, NAND, NOR, XNOR, inverter, and buffer - selected solely by hardwiring inputs A, B, and C to VCC or GND per the function table in Section 7.1 of the datasheet. No clock, enable, or programming interface is required; configuration is static and permanent per PCB layout.

Does the 74AUP1G57GS,132 support level shifting between different supply voltages?

Yes - its inputs tolerate up to 3.6 V regardless of VCC setting (down to 0.8 V), enabling safe interfacing of higher-voltage signals (e.g., 3.3 V GPIO) into lower-voltage domains (e.g., 1.8 V MCU I/O). Output swing remains rail-to-rail relative to its own VCC, so external translation may be needed for bidirectional level shifting.

How does the IOFF feature behave during power sequencing?

When VCC drops to 0 V, the IOFF circuit forces the Y output into high-impedance state, limiting leakage to ±0.75 μA even if external signals remain active on Y or inputs. This prevents back-current flow that could disrupt upstream drivers or violate system power-state assumptions during controlled shutdown or hot-plug events.

Can the 74AUP1G57GS,132 replace discrete logic gates in existing designs?

Yes - its 1.0 mm × 1.0 mm XSON6 footprint matches common 0402 passives and smaller than most SOT-23 logic ICs. With identical pinout to other 74AUP1Gxx variants in SOT1202, it enables drop-in replacement where Schmitt-trigger noise immunity, ultra-low ICC, or IOFF are needed - provided A/B/C wiring matches the target function's truth table.