Diodes Incorporated 74AUP1G58FZ4-7

Overview

74AUP1G58FZ4-7 from Diodes Incorporated is a single 3-input configurable multiple-function logic gate in X2-DFN1410-6 package, supporting AND, OR, NAND, NOR, XOR, inverter, and buffer functions via input pin configuration. It operates from 0.8V to 3.6V, features ±4mA output drive at 3.0V, Schmitt-trigger inputs (950mV typical hysteresis at V_CC = 3.0V), and IOFF partial power-down protection. It is used in battery-powered portable electronics for voltage-level shifting and signal conditioning.

For engineers reviewing the 74AUP1G58FZ4-7 datasheet, 74AUP1G58FZ4-7 pinout, 74AUP1G58FZ4-7 application, or 74AUP1G58FZ4-7 equivalent, key selection criteria include ultra-low static current (<0.9µA), 3.6V-tolerant inputs in mixed-voltage systems, configurable logic without external components, and DFN1410 footprint compatibility with space-constrained PCB layouts.

Technical Context

This device implements a programmable 3-input combinational logic cell where the output Y is determined by all eight possible combinations of inputs A, B, and C - enabling user-defined Boolean functions without external gates. Its Schmitt-trigger inputs provide noise immunity and tolerate slow-rising/falling signals, with hysteresis ranging from 0.07V (0.8V supply) to 1.31V (3.0V supply).

The IOFF circuit actively disables outputs during power-down, preventing back-current flow when V_CC = 0V while inputs remain biased at 0–3.6V. It supports partial-power-down operation per JESD78 Class I latch-up immunity (>100mA) and meets JESD22 ESD ratings: >2000V HBM, >1000V CDM, >200V MM.

Key Specifications

Pinout & Package

X2-DFN1410-6 (1.4mm × 1.0mm × 0.4mm, 0.5mm pitch, leadless, RoHS-compliant) with exposed thermal pad. Pin 1 marked by chamfered corner.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar configurable logic gate applications.

Compared with SN74LVC1G58DBVR and NC7SZ58P5X, the 74AUP1G58FZ4-7 uniquely combines Schmitt-trigger noise rejection, IOFF isolation, and sub-µA static current - making it the sole option for battery-critical, mixed-voltage, and glitch-prone environments.

Availability

74AUP1G58FZ4-7 is available at Aetrix Electronics and suitable for USB-C interface design, IoT sensor node power sequencing, industrial HMI button conditioning, and low-power display backlight control requiring stable component supply across multi-year production cycles.

Supply support for 74AUP1G58FZ4-7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global semiconductor company specializing in discrete, analog, and logic solutions for power management, signal integrity, and connectivity applications.

The 74AUP logic family targets ultra-low-power portable and battery-operated devices, emphasizing sub-1V operation, nanowatt static consumption, and robust noise immunity for next-generation wearables and edge sensors.

FAQ

What logic functions can be implemented with the 74AUP1G58FZ4-7?

The device supports eight configurations: 2-input AND, OR, NAND, NOR, XOR, inverter, non-inverting buffer, and 2-input NAND/OR with both inputs inverted. Function selection is achieved by hardwiring inputs A, B, and C to V_CC or GND per the datasheet's Function Selection Table - no external programming or configuration pins are needed.

Does the 74AUP1G58FZ4-7 support level-shifting between different voltage domains?

Yes. Its inputs tolerate up to 3.6V regardless of V_CC (0.8–3.6V), enabling reliable interfacing between higher-voltage peripherals (e.g., 3.3V sensors) and lower-voltage processors (e.g., 1.2V SoCs). The output swings rail-to-rail within the V_CC domain, providing clean level translation without external resistors or translators.

How does the IOFF feature protect the system during partial power-down?

When V_CC is removed, the IOFF circuit disconnects the output Y from internal nodes, limiting leakage to ±0.2µA maximum. This prevents current from flowing backward into a powered subsystem (e.g., from a 3.3V bus into a 0V logic domain), eliminating risk of latch-up or unintended activation of downstream circuitry during sleep modes.

Is the X2-DFN1410-6 package compatible with standard reflow profiles?

Yes. The X2-DFN1410-6 package is qualified for IPC/JEDEC J-STD-020D moisture sensitivity level 1 (MSL1) and withstands peak reflow temperatures up to 260°C. Its 0.5mm pitch and 0.4mm height allow use with standard stencil thicknesses (0.1mm) and Type 4 solder paste, with recommended preheat (150°C), soak (180°C), and ramp rates per Diodes' AP02001 layout guide.