Nexperia USA Inc. 74AUP1G58GM,115

Overview

74AUP1G58GM,115 from Nexperia is a single-channel, low-power configurable logic gate with Schmitt-trigger inputs, supporting AND, OR, NAND, NOR, XOR, inverter, and buffer functions via 3-bit configuration (A/B/C inputs). It operates across 0.8 V to 3.6 V supply, delivers ≤0.9 μA max ICC at −40 °C to +125 °C, and features IOFF partial power-down protection. It is used in battery-powered sensor interfaces and portable MCU peripheral logic where voltage flexibility and ultra-low static power are critical.

For engineers reviewing the 74AUP1G58GM,115 datasheet, 74AUP1G58GM,115 pinout, 74AUP1G58GM,115 application, or 74AUP1G58GM,115 equivalent, key selection criteria include its 6-terminal XSON6 (SOT886) package, Schmitt-trigger noise immunity, sub-1 μA supply current, IOFF-enabled system-level power sequencing, and configurable function mapping without external components.

Technical Context

The 74AUP1G58GM,115 implements a programmable logic cell using three input pins (A, B, C) to select one of seven standard logic functions via internal hardwired decoding-no configuration register or clock required. Its Schmitt-trigger inputs provide hysteresis (VH = 0.07–1.31 V depending on VCC), enabling robust operation with slow or noisy signals.

It supports true partial power-down via IOFF circuitry that disables output drivers when VCC = 0 V, limiting backflow current to ±0.75 μA maximum. All inputs tolerate up to 3.6 V regardless of VCC, allowing mixed-voltage interfacing between 1.2 V, 1.8 V, and 3.3 V domains.

Key Specifications

Pinout & Package

XSON6 plastic extremely thin small outline package (SOT886); no leads; 6 terminals; body dimensions 1.0 × 1.45 × 0.5 mm; thermal pad not present; pin 1 index located on lower-left corner below marking code "aK".

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar configurable logic gate applications.

Compared with 74LVC1G58GW,125 and SN74LVC1G97DBVR, the 74AUP1G58GM,115 uniquely combines sub-1.5 μA ICC, guaranteed IOFF, Schmitt inputs, and −40 °C to +125 °C operation in a 1.0 × 1.45 mm XSON6 package-making it the only choice for high-reliability, energy-constrained embedded systems requiring mixed-voltage interoperability.

Availability

74AUP1G58GM,115 is available at Aetrix Electronics and suitable for industrial sensor interfaces, portable MCU peripheral logic, automotive body control modules, and medical diagnostic handhelds requiring stable component supply across extended temperature ranges and ultra-low power budgets.

Supply support for 74AUP1G58GM,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable logic, analog, and discrete components optimized for efficiency, miniaturization, and robustness in demanding applications.

The 74AUP1G58GM,115 belongs to Nexperia's Advanced Ultra-low Power (AUP) logic family, designed specifically for energy-sensitive systems such as battery-powered IoT sensors, wearables, and automotive ECUs where nanowatt static power and wide-voltage operation are mandatory.

FAQ

What logic functions can the 74AUP1G58GM,115 implement?

The 74AUP1G58GM,115 implements seven fixed logic functions-AND, OR, NAND, NOR, XOR, inverter, and buffer-selected solely by tying its three inputs (A, B, C) to VCC or GND per the function table in Section 7 of the datasheet. No programming interface, clock, or external components are needed; configuration is static and hardware-defined.

Does the 74AUP1G58GM,115 require external pull-up or pull-down resistors?

No. All inputs accept direct connection to VCC or GND without external biasing. The device's internal design ensures valid logic levels across the full 0.8–3.6 V supply range, and Schmitt-trigger inputs eliminate need for external hysteresis components-even with slow or noisy signals.

How does IOFF protect the device during partial power-down?

When VCC = 0 V, the IOFF circuitry actively disables the output driver, limiting leakage current through Y to ±0.75 μA maximum. This prevents reverse current flow from powered downstream circuits into the unpowered IC, avoiding latch-up risk and ensuring safe hot-plug operation in modular systems.

Can the 74AUP1G58GM,115 interface with 5 V logic?

No. While inputs tolerate up to 3.6 V, the absolute maximum VCC is +4.6 V and recommended operating VCC caps at 3.6 V. Driving it from 5 V logic violates voltage ratings. For 5 V systems, use 74LVC1G58GW,125 instead-but note its higher power and lack of Schmitt inputs.