Nexperia USA Inc. 74AUP1G58GW,125

Overview

74AUP1G58GW,125 from Nexperia is a single-gate configurable logic device with Schmitt-trigger inputs, supporting AND, OR, NAND, NOR, XOR, inverter, and buffer functions via 3-bit configuration (A/B/C inputs). It operates from 0.8 V to 3.6 V, delivers ≤0.9 μA max ICC at 125 °C, and features IOFF partial power-down protection. It is used in low-power sensor interface signal conditioning and battery-powered IoT node logic adaptation.

For engineers reviewing the 74AUP1G58GW,125 datasheet, 74AUP1G58GW,125 pinout, 74AUP1G58GW,125 application, or 74AUP1G58GW,125 equivalent, key selection criteria include its ultra-low static current across voltage range, Schmitt-trigger noise immunity, IOFF-enabled system-level power sequencing, and TSSOP6 package compatibility with space-constrained PCB layouts.

Technical Context

The 74AUP1G58GW,125 implements a single-output, three-input configurable gate using CMOS logic with Schmitt-trigger input thresholds (VT+ = 1.88 V, VT− = 0.88 V at VCC = 3.0 V) and hysteresis (VH = 1.0 V), enabling robust noise rejection in noisy environments. Its function is determined by static logic levels applied to A, B, and C pins per Table 4 and Table 5 - no clock or control bus required.

IOFF circuitry actively disables output leakage when VCC = 0 V (≤±0.75 μA), preventing backflow current during partial power-down. Propagation delay ranges from 1.6 ns (VCC = 3.3 V, CL = 5 pF) to 24.1 ns (VCC = 1.2 V, CL = 30 pF), scaling predictably with supply and load.

Key Specifications

Pinout & Package

TSSOP6 plastic thin shrink small outline package (SOT363-2); 6-lead, 1.25 mm body width, 0.65 mm pitch; lead-free and RoHS compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar configurable logic gate applications.

Compared with SN74LVC1G58DBVR and 74LVC1G97GW,125, the 74AUP1G58GW,125 uniquely combines sub-1 μA static current, Schmitt-trigger noise immunity, and IOFF in a TSSOP6 package-making it optimal for battery-critical, noise-prone, and multi-rail embedded systems where power integrity and signal fidelity are co-constrained.

Availability

74AUP1G58GW,125 is available at Aetrix Electronics and suitable for industrial sensor interfaces, portable device power sequencing, automotive body control modules, and IoT edge node logic adaptation requiring stable component supply across extended temperature and low-power operating conditions.

Supply support for 74AUP1G58GW,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, analog, and MOSFET solutions optimized for power and signal integrity.

The 74AUP1G58GW,125 belongs to the Advanced Ultra-low Power (AUP) logic family, designed specifically for energy-constrained applications demanding nanowatt static operation, robust noise immunity, and seamless integration into mixed-voltage embedded systems.

FAQ

What logic functions can the 74AUP1G58GW,125 implement?

The 74AUP1G58GW,125 implements seven logic functions - AND, OR, NAND, NOR, XOR, inverter, and buffer - selected by static logic levels applied to its three configuration inputs (A, B, C). The function is defined by the truth table in Section 7 of the datasheet and requires no clock or programming interface; configuration is set at power-on and remains static during operation.

Does the 74AUP1G58GW,125 require external pull-up or pull-down resistors on its inputs?

No. All inputs (A, B, C) can be directly tied to VCC or GND without external resistors. The device's Schmitt-trigger inputs have defined threshold voltages (VT+ and VT−) and hysteresis, ensuring reliable logic interpretation even with slow or floating transitions. External resistors are unnecessary unless specific biasing is needed for unused inputs in custom configurations.

How does IOFF functionality protect the device during partial power-down?

When VCC = 0 V, the IOFF circuitry places the Y output in high-impedance state, limiting leakage current to ≤±0.75 μA. This prevents damaging backflow current from powered downstream circuits (e.g., 3.3 V buses) into the unpowered device, enabling safe power sequencing in multi-rail systems such as battery-backed sensors or modular IoT hardware.

Can the 74AUP1G58GW,125 operate reliably at 0.8 V supply voltage?

Yes. The device is fully specified from 0.8 V to 3.6 V, with propagation delay of 22.8 ns (typical) and VOH ≥ VCC − 0.11 V at 0.8 V and +125 °C. Its ultra-low ICC (<1.4 μA) and Schmitt-trigger inputs maintain functional integrity at minimum VCC, making it suitable for energy-harvesting systems where supply voltage may dip near 0.8 V during low-light or low-vibration conditions.