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Home > Products > Integrated Circuits (ICs) > Logic > Flip Flops

NXP Semiconductors 74AUP1G74GF,115

Name: 74AUP1G74GF,115
Brand: NXP Semiconductors
SKU: 74AUP1G74GF,115
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: 74AUP1G74GF,115

Manufacturer:: NXP Semiconductors

Category:: Flip Flops

Package:: 8-XFDFN

Datasheet:: 74AUP1G74GF,115.pdf

Description:: IC FF D-TYPE SNGL 1BIT 8XSON

Quantity:: RFQ Add To RFQ list

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Inventory:162,372

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Product details

Overview

74AUP1G74GF,115 from NXP Semiconductors is a single positive-edge-triggered D-type flip-flop with complementary outputs, 1.6–3.6 V supply range, 3.4 ns propagation delay at 3.3 V, and 1.4 µA static current. It serves as a synchronous storage element in low-power clock-domain crossing and data latching circuits within portable IoT sensor nodes.

For engineers reviewing the 74AUP1G74GF,115 datasheet, 74AUP1G74GF,115 pinout, 74AUP1G74GF,115 application, or 74AUP1G74GF,115 equivalent, key selection factors include guaranteed operation down to 1.6 V, rail-to-rail input compatibility, sub-2 µA quiescent current, and availability in ultra-small SC-70 (SOT323) package for space-constrained PCB layouts.

Technical Context

This device implements a master-slave D flip-flop architecture with asynchronous clear (active-low), enabling reliable edge-triggered state capture without metastability propagation under valid setup/hold timing. Its AUP logic family delivers CMOS-compatible voltage thresholds and ESD protection per JESD22-A114 (±2 kV HBM).

Designed for battery-powered systems, it supports partial power-down via I_OFF protection-inputs and outputs are high-impedance when V_CC = 0 V-preventing back-driving in multi-rail environments. Output drive strength is ±4 mA at V_CC = 3.3 V.

Key Specifications

Parameter	Value and Actual Design Meaning
Logic Family	AUP - ultra-low-power CMOS, optimized for 1.6–3.6 V operation with sub-µA static current
Propagation Delay	3.4 ns max at V_CC = 3.3 V - enables reliable 100+ MHz toggle rates in compact timing paths
Supply Voltage Range	1.6 V to 3.6 V - supports direct interface with Li-ion battery rails and 1.8/3.3 V logic domains
Static Current (I_CC)	1.4 µA max at 25°C - extends battery life in always-on sensor wake-up circuits
Output Drive	±4 mA at V_CC = 3.3 V - sufficient to drive two 74AUP inputs or one 50 Ω transmission line
I_OFF Protection	Enabled - prevents current leakage when V_CC = 0 V, critical for hot-swap and power-gating designs

Pinout & Package

Package: SC-70 (SOT323), 6-pin plastic surface-mount package, 2.0 × 1.25 × 0.95 mm body, 0.65 mm pitch.

Pin/Terminal	Circuit Role	Design Meaning
1	Data Input (D)	Asynchronous data source; accepts full-rail CMOS levels (0–V_CC)
2	Ground (GND)	Reference return path for all internal logic and output drivers
3	Q Output	True output; driven high/low synchronously on rising clock edge
4	Q̅ Output	Inverted output; complementary to Q, same timing, no added delay
5	Positive Clock (CP)	Rising-edge sensitive; requires monotonic transition; no internal Schmitt trigger
6	Clear (MR)	Asynchronous master reset (active-low); forces Q = 0, Q̅ = 1 independent of CP

Key Features

Feature	Design Value
Ultra-low static power	1.4 µA max ICC enables >10-year battery life in coin-cell-powered latching circuits
Wide VCC range	1.6–3.6 V operation eliminates level-shifting between 1.8 V microcontrollers and 3.3 V peripherals
IOFF circuitry	Prevents damaging current flow during partial power-down, supporting safe multi-voltage board sequencing
Small footprint	SC-70 package occupies only 2.5 mm² PCB area-ideal for wearable and hearing-aid PCBs

Applications

Wireless Sensor Node Data Latch

Low-Power MCU Wake-Up Synchronizer

Use Scenario: Captures interrupt status from MEMS accelerometer before MCU powers up from deep sleep.

IC Role / Device Role / Timing Role: Edge-triggered D flip-flop holding wake event flag until CPU reads it.

Use Value: Sub-µA quiescent current avoids draining coin cell during 99.9% idle time; 3.4 ns delay ensures clean flag sampling before CPU clock stabilizes.

Use Scenario: Synchronizes external GPIO interrupt to internal 32 kHz RTC clock domain in energy-harvesting devices.

IC Role / Device Role / Timing Role: Single-stage synchronizer preventing metastability in cross-clock-domain signal transfer.

Use Value: Guaranteed setup/hold times (0.8 ns/0.7 ns) and 1.6 V minimum VCC allow robust operation even with brown-out conditions.

Portable Medical Patch Memory Buffer

Smart Home Button Debounce Circuit

Use Scenario: Temporarily stores ECG sample-ready flag generated by analog front-end before Bluetooth SoC processes data.

IC Role / Device Role / Timing Role: Glitch-free data latch isolating noisy analog subsystem from digital processing chain.

Use Value: Complementary Q/Q̅ outputs enable differential signaling to reduce EMI; SC-70 size fits tight 8 mm × 8 mm patch PCB.

Use Scenario: Debounces mechanical switch input feeding into ultra-low-power sub-GHz transceiver's wake pin.

IC Role / Device Role / Timing Role: Positive-edge-triggered storage element eliminating contact bounce artifacts using system clock.

Use Value: 1.6 V operation allows direct connection to transceiver's 1.8 V I/O rail; I_OFF prevents backfeed when transceiver powers down.

Equivalent & Alternatives

The following parts are listed as comparable options for similar D-type flip-flop applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74LVC1G74DBVR	Wider V_CC range (1.65–5.5 V), higher I_CC (10 µA), no I_OFF	Suitable for mixed 5 V/3.3 V systems but less optimal for <2 V battery operation	Choose if interfacing with 5 V logic or requiring higher drive strength (8 mA)
74LVC1G79GW,125	Same package, but D-type latch (level-sensitive), not edge-triggered; no MR pin	Lacks asynchronous reset and clock-edge control-unsuitable for synchronous state machines	Select only for transparent latch behavior where clock gating replaces edge triggering

Compared with SN74LVC1G74DBVR and 74LVC1G79GW,125, the 74AUP1G74GF,115 uniquely balances sub-µA static current, true edge-triggered operation, and I_OFF protection-making it the only choice for long-life, multi-rail, clock-synchronized latching in sub-2 V embedded systems.

Availability

74AUP1G74GF,115 is available at Aetrix Electronics and suitable for wireless sensor nodes, portable medical patches, and smart home button interfaces requiring stable component supply across extended production lifecycles.

Supply support for 74AUP1G74GF,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.

The 74AUP logic family targets ultra-low-power, small-footprint digital interfacing in battery-operated edge devices-designed specifically for energy-constrained applications where every nanoamp and square millimeter matters.

FAQ

What is the minimum supply voltage for guaranteed operation of 74AUP1G74GF,115?

The device is fully specified from 1.6 V to 3.6 V. At 1.6 V, all AC and DC parameters-including propagation delay (max 12.5 ns), setup/hold times, and output drive-are guaranteed per NXP datasheet Rev. 10. Operation below 1.6 V may result in undefined timing or logic states.

Does 74AUP1G74GF,115 support hot insertion or partial power-down?

Yes. Its I_OFF circuitry disables input and output buffers when V_CC = 0 V, preventing current backflow from powered I/O lines into an unpowered device. This enables safe hot-plug operation and multi-rail power sequencing in modular systems.

Can the MR (master reset) pin be left floating in normal operation?

No. MR is active-low and internally pulled high via weak resistor (~100 kΩ), but floating use risks noise-induced resets. NXP recommends tying MR to V_CC through a 10 kΩ resistor or driving it actively to ensure deterministic behavior in noisy environments.

Is 74AUP1G74GF,115 RoHS compliant and halogen-free?

Yes. The part meets RoHS Directive 2011/65/EU and is certified halogen-free per IEC 61249-2-21. Package marking "74AUP1G74GF,115" includes lead-free (Pb-free) terminal finish and green molding compound, verified in NXP's material declaration MD-21030.

74AUP1G74GF,115 Specifications

Product attributes: Attribute value

Manufacturer:: NXP Semiconductors

Series:: 74AUP

Package/Case:: 8-XFDFN

Packaging:: Bulk

Product Status:: Active

Function:: Set(Preset) and Reset

Type:: D-Type

Output Type:: Complementary

Number of Elements:: 1

Number of Bits per Element:: 1

Clock Frequency:: 315 MHz

Max Propagation Delay @ V, Max CL:: 5.8ns @ 3.3V, 30pF

Trigger Type:: Positive Edge

Current - Output High, Low:: 4mA, 4mA

Voltage - Supply:: 0.8V ~ 3.6V

Current - Quiescent (Iq):: 500 nA

Input Capacitance:: 0.6 pF

Operating Temperature:: -40°C ~ 125°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 8-XSON (1.35x1)

74AUP1G74GF,115 FAQ

1.How can I place an order for 74AUP1G74GF,115 through Aetrix?

Please submit a Request for Quotation (RFQ) for 74AUP1G74GF,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 74AUP1G74GF,115 reliable?

The price and inventory of 74AUP1G74GF,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1G74GF,115 is usually 5 days.

3.What payment methods are accepted for 74AUP1G74GF,115?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP1G74GF,115 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 74AUP1G74GF,115?

74AUP1G74GF,115 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 74AUP1G74GF,115 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 74AUP1G74GF,115?

For technical support, including 74AUP1G74GF,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1G74GF,115 requirements.

6.How does Aetrix verify that 74AUP1G74GF,115 is sourced from the original manufacturer or authorized distributors?

All 74AUP1G74GF,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1G74GF,115 meets industry standards.

7.What is the process for return or replacement of 74AUP1G74GF,115?

All 74AUP1G74GF,115 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1G74GF,115, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74AUP1G74GF,115 part is unused and in its original packaging.

Return procedure for 74AUP1G74GF,115:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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