Nexperia USA Inc. 74AUP1G74GN,115

Overview

74AUP1G74GN,115 from Nexperia is a single positive-edge-triggered D-type flip-flop with asynchronous set (SD) and reset (RD) inputs, complementary Q and Q̅ outputs, and Schmitt-trigger inputs for noise immunity. It operates across 0.8 V to 3.6 V supply, delivers ≤0.9 μA max ICC at 25 °C, supports −40 °C to +125 °C ambient, and features IOFF circuitry for partial power-down protection in battery-powered IoT sensor nodes.

For engineers reviewing the 74AUP1G74GN,115 datasheet, 74AUP1G74GN,115 pinout, 74AUP1G74GN,115 application, or 74AUP1G74GN,115 equivalent, key selection criteria include its ultra-low static current, guaranteed setup/hold timing down to 0.8 V VCC, Schmitt-trigger input tolerance for slow-rising control signals, and XSON8 (SOT1116) package compatibility with high-density PCB layouts.

Technical Context

This device implements a master-slave D flip-flop architecture synchronized on the LOW-to-HIGH clock transition, with priority-governed asynchronous set and reset that override clocked data storage. Its Schmitt-trigger inputs provide hysteresis (typ. 0.3 V at VCC = 3.3 V), enabling robust operation with slow or noisy control lines such as push-button debouncing or microcontroller GPIO wake-up signals.

The IOFF circuit disables outputs when VCC = 0 V, preventing backflow current during hot-insertion or multi-rail power sequencing-critical for portable medical monitors and industrial fieldbus interface modules where partial power-down is mandated by system-level energy budgets.

Key Specifications

Pinout & Package

XSON8 package (SOT1116): extremely thin small outline, no leads, 8 terminals, body dimensions 1.2 mm × 1.0 mm × 0.35 mm, thermal pad optional, pin 1 indicator located below marking code "54" in lower-left corner.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar D-type flip-flop applications.

Compared with SN74LVC1G74DBVR and 74LVC1G79GW,125, the 74AUP1G74GN,115 uniquely combines ultra-low ICC, IOFF, Schmitt inputs, and full 0.8–3.6 V operation-making it the sole choice for energy-constrained, mixed-voltage, or EMI-prone embedded designs requiring guaranteed async control and power sequencing safety.

Availability

74AUP1G74GN,115 is available at Aetrix Electronics and suitable for industrial sensor interfaces, wearable health monitors, automotive body control units, and smart home hub controllers requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74AUP1G74GN,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable, and efficient logic, discrete, and MOSFET solutions for automotive, industrial, and consumer markets.

The 74AUP (Advanced Ultra-low Power) product line targets battery-operated and energy-sensitive applications, emphasizing minimal static/dynamic power, wide supply flexibility, and robust signal integrity in space-constrained designs.

FAQ

What is the minimum recommended VCC for guaranteed operation at −40 °C to +125 °C?

The datasheet specifies 0.8 V as the absolute minimum VCC across the full temperature range. At −40 °C to +125 °C, VIH remains ≥0.75×VCC and VIL ≤0.30×VCC, ensuring correct logic interpretation even at 0.8 V. No derating is required beyond the published limits.

Can the 74AUP1G74GN,115 drive a 50 pF load reliably?

No-the device is characterized up to 30 pF load capacitance. At CL = 30 pF and VCC = 3.3 V, tpd increases to 7.3 ns max and fmax drops to 190 MHz. Driving 50 pF exceeds design validation and may cause timing violations or excessive output rise/fall times; use a buffer stage for heavier loads.

How does the IOFF feature behave when VCC ramps from 0 V to nominal?

IOFF activates when VCC falls below ~0.2 V and deactivates once VCC rises above ~0.4 V. During ramp-up, outputs remain in high-Z until VCC crosses the enable threshold, then resume normal operation after power-on reset timing (trec ≤ 0.1 ns). This prevents glitching during brown-out conditions.

Is the marking code "54" unique to the GN package variant?

Yes-per Table 2, "54" is assigned exclusively to 74AUP1G74GN, 74AUP1G74GS, and 74AUP1G74GX variants. The GN package (SOT1116) is distinguished by its 1.2 mm × 1.0 mm body size and 0.35 mm height, confirmed in Figure 9 of the datasheet.