Nexperia USA Inc. 74AUP1G74GT,115

Overview

74AUP1G74GT,115 from Nexperia is a single positive-edge-triggered D-type flip-flop with asynchronous set (SD) and reset (RD) inputs, complementary Q/Q̅ outputs, Schmitt-trigger inputs for noise immunity, and full IOFF support for partial power-down operation across 0.8 V to 3.6 V supply. It delivers ultra-low static current (≤1.4 μA at −40 °C to +125 °C), propagation delays as low as 1.2 ns at 3.6 V/CL = 5 pF, and operates reliably in automotive body control modules requiring robust level-shifting and glitch-free state retention during rail transitions.

For engineers reviewing the 74AUP1G74GT,115 datasheet, 74AUP1G74GT,115 pinout, 74AUP1G74GT,115 application, or 74AUP1G74GT,115 equivalent, this device is selected for low-voltage synchronous data latching in battery-powered IoT sensors, I²C bus signal conditioning, and mixed-supply interface bridging where sub-1-μA quiescent current and ±0.2 μA IOFF leakage are critical design constraints.

Technical Context

This flip-flop implements edge-triggered synchronous storage with priority-governed asynchronous set/reset logic: SD and RD override clocked behavior when asserted low, and both must be high for CP-triggered D-to-Q transfer. Its Schmitt-trigger inputs ensure reliable operation with slow-rising signals up to 200 ns/V input transition rate, eliminating external hysteresis components.

The IOFF circuit actively disables outputs when VCC = 0 V, blocking backflow current into powered-down system rails-enabling safe hot-swap and multi-rail power sequencing. All DC and AC specifications-including VIH/VIL thresholds, tpd, tsu/th, and fmax-are fully characterized from −40 °C to +125 °C across the entire 0.8 V–3.6 V VCC range per JEDEC standards JESD8-12 through JESD8C.

Key Specifications

Pinout & Package

XSON8 plastic extremely thin small outline package (SOT833-1); no leads; 8 terminals; body dimensions 1.0 mm × 1.95 mm × 0.5 mm; thermal pad optional; moisture sensitivity level MSL3.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar D-type flip-flop applications.

Compared with SN74LVC1G74DCKR and 74LVC1G79GW,125, the 74AUP1G74GT,115 uniquely combines sub-1-μA static current, true IOFF, Schmitt-triggered inputs, and full 0.8–3.6 V operation-making it the sole option for battery-constrained, multi-rail, or automotive-grade D-latch requirements.

Availability

74AUP1G74GT,115 is available at Aetrix Electronics and suitable for automotive body electronics, industrial sensor interfaces, battery-powered IoT endpoints, and mixed-voltage FPGA glue logic requiring stable component supply across extended temperature and voltage ranges.

Supply support for 74AUP1G74GT,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable, and efficient logic, analog, and discrete components for automotive, industrial, and consumer markets.

The 74AUP (Advanced Ultra-low Power) product line targets ultra-low-power digital logic applications demanding sub-microamp quiescent current, wide VCC range, and robust IOFF functionality for modern energy-conscious system designs.

FAQ

What is the minimum recommended VCC for guaranteed operation at −40 °C?

The 74AUP1G74GT,115 is fully specified down to 0.8 V across −40 °C to +125 °C. At −40 °C, VIH remains ≥0.75 × VCC and VOL ≤0.50 V at IO = 4.0 mA, ensuring reliable logic-level compatibility with 0.8 V-core processors and energy-harvesting PMICs without derating.

Can SD and RD be tied together and driven by a single control signal?

Yes-SD and RD share identical electrical characteristics (VIH/VIL, drive strength, timing). Tying them enables simultaneous set/reset control, but note that asserting both low results in undefined Q/Q̅ outputs per the function table; use only in configurations where this state is avoided or externally managed.

Does the IOFF feature require external pull-up/down resistors on Q and Q̅?

No. When VCC = 0 V, IOFF forces Q and Q̅ into high-impedance states regardless of input voltages. External resistors are unnecessary unless required for system-level default-state biasing during complete power removal-per application schematics, not device specification.

How does Schmitt-trigger action improve noise immunity in real-world layouts?

Schmitt-trigger inputs provide ≥150 mV hysteresis at 3.3 V, rejecting common-mode noise spikes ≤150 mV and allowing clean sampling of signals with rise/fall times up to 200 ns/V-critical for long PCB traces near motors, relays, or switching regulators where RC filtering would degrade timing margins.