Nexperia USA Inc. 74AUP1G74GXX

Overview

74AUP1G74GXX from Nexperia is a single positive-edge-triggered D-type flip-flop with asynchronous set (SD) and reset (RD) inputs, complementary Q and Q̅ outputs, and Schmitt-trigger inputs for noise immunity. It operates across 0.8 V to 3.6 V supply, delivers ≤0.9 μA max ICC at 25 °C, supports -40 °C to +125 °C ambient, and features IOFF circuitry for partial power-down protection in battery-powered logic interfaces.

For engineers reviewing the 74AUP1G74GXX datasheet, 74AUP1G74GXX pinout, 74AUP1G74GXX application, or 74AUP1G74GXX equivalent, key selection criteria include its ultra-low static current, sub-1 ns setup/hold times at 3.3 V, 550 MHz max clock frequency, and compatibility with mixed-voltage I/O systems down to 0.8 V.

Technical Context

This device implements a master-slave D flip-flop architecture with fully asynchronous active-low set and reset controls that override clocked data storage. Its Schmitt-trigger inputs tolerate slow-rising signals and provide hysteresis of ≥0.3 V typical across VCC = 1.2 V–3.6 V, enabling robust operation in noisy digital environments.

The IOFF circuit ensures output disable and backflow current prevention when VCC = 0 V, satisfying JEDEC JESD8-12 through JESD8C compliance across five voltage bands. Propagation delays are specified from 1.2 ns (CP→Q, CL = 5 pF, VCC = 3.3 V) to 4.4 ns (CL = 30 pF), with tSU/tH as low as 0.4 ns/0.1 ns under same conditions.

Key Specifications

Pinout & Package

X2SON8 package (SOT1233-2): plastic thermal-enhanced extremely thin small outline, no leads, 8 terminals, body size 1.35 × 0.8 × 0.32 mm, pin 1 indicator located below marking code in lower-left corner.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar D-type flip-flop applications.

Compared with SN74LVC1G74DBVR and 74LVC1G74GW,125, the 74AUP1G74GXX provides superior low-power operation, wider voltage flexibility, built-in IOFF, and Schmitt-trigger inputs-making it the only choice for energy-constrained, mixed-voltage, or thermally demanding designs.

Availability

74AUP1G74GXX is available at Aetrix Electronics and suitable for industrial PLC I/O expansion, automotive body control units, portable medical sensor hubs, and low-power wireless nodes requiring stable component supply across extended temperature and voltage ranges.

Supply support for 74AUP1G74GXX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable, and efficient logic, analog, and MOSFET solutions for automotive, industrial, and consumer markets.

The 74AUP (Advanced Ultra-low Power) product line targets ultra-low-power digital logic applications requiring sub-microamp static current, wide VCC scalability, and robust operation in thermally constrained or battery-powered systems.

FAQ

What is the minimum recommended VCC for guaranteed operation?

The 74AUP1G74GXX is fully specified from 0.8 V to 3.6 V. At VCC = 0.8 V, it maintains functional operation with tPD ≤ 25.4 ns (CL = 5 pF) and VIH/VIL thresholds scaled to 70% and 30% of VCC respectively-enabling direct integration with sub-1 V microcontrollers and energy-harvesting PMICs.

How does the IOFF feature protect the device during power sequencing?

When VCC = 0 V, the IOFF circuit disables all outputs into high-impedance state and limits VI/O leakage to ±0.75 μA. This prevents reverse current flow from powered downstream logic (e.g., 3.3 V FPGA I/O) into the unpowered flip-flop, eliminating risk of latch-up or damage during staggered rail startup/shutdown.

Can SD and RD be used simultaneously without conflict?

Yes: per the function table, asserting both SD and RD LOW produces a defined metastable-free output state (Q = H, Q̅ = H). This "invalid" state is electrically stable and resolves to valid Q/Q̅ on the next valid CP edge or when either SD or RD returns HIGH-providing predictable behavior during system reset assertion.

Is the X2SON8 (SOT1233-2) package compatible with standard reflow profiles?

Yes: the SOT1233-2 package is qualified for IPC/JEDEC J-STD-020 moisture sensitivity level 1 (MSL-1) and supports peak reflow temperatures up to 260 °C. Its 0.32 mm height and thermal-enhanced construction ensure reliable solder joint formation and minimal warpage during standard lead-free reflow cycles.