Nexperia USA Inc. 74AUP1G79GV,125

Overview

74AUP1G79GV,125 from Nexperia is a single positive-edge-triggered D-type flip-flop in SC-74A (SOT753) package, operating from 0.8 V to 3.6 V supply, with 0.9 μA max ICC, 5-pin configuration, and -40 °C to +125 °C temperature range-used for clock-synchronized data latching in ultra-low-power sensor interface and battery-powered IoT node timing paths.

For engineers reviewing the 74AUP1G79GV,125 datasheet, 74AUP1G79GV,125 pinout, 74AUP1G79GV,125 application, or 74AUP1G79GV,125 equivalent, key selection criteria include its sub-1 μA static current, IOFF-enabled partial power-down capability, Schmitt-trigger input tolerance for slow-rising control signals, and guaranteed operation down to 0.8 V for energy-harvesting systems.

Technical Context

This device implements a synchronous edge-triggered storage element with non-inverting Q output, where data at the D-input meeting setup/hold timing on the LOW-to-HIGH clock transition is captured and held until the next valid edge. Its Schmitt-trigger inputs provide hysteresis (typ. 0.3 V at VCC = 1.2 V), enabling robust operation with noisy or slow-ramping control lines.

The IOFF circuit actively disables outputs when VCC = 0 V, limiting backflow current to ±0.75 μA max, and the device complies with JEDEC standards JESD8-12 through JESD8-C across its full voltage range-ensuring interoperability in mixed-voltage logic domains and hot-swap-capable subsystems.

Key Specifications

Pinout & Package

74AUP1G79GV,125 uses the SC-74A (SOT753) plastic surface-mounted package: 5-lead, body size 3.1 mm × 1.7 mm × 1.3 mm, pin pitch 0.65 mm, exposed pad not present.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar D-type flip-flop applications.

Compared with SN74LVC1G79DBVR, 74AUP1G79GV,125 delivers 11× lower static current and true zero-VCC isolation; versus 74LVC1G79GW,125, it offers identical functionality in a smaller, thermally superior SC-74A package optimized for space-constrained designs.

Availability

74AUP1G79GV,125 is available at Aetrix Electronics and suitable for industrial sensor interfaces, low-power wearable controllers, and automotive body control modules requiring stable component supply across extended temperature ranges and long product lifecycles.

Supply support for 74AUP1G79GV,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance logic, discrete, and MOSFET solutions with focus on efficiency, reliability, and miniaturization for automotive, industrial, and mobile markets.

The 74AUP (Advanced Ultra-low Power) logic family targets energy-constrained applications demanding sub-microamp quiescent current, wide voltage operation, and robust signal integrity-designed specifically for battery-powered and energy-harvesting systems.

FAQ

What is the minimum supply voltage for guaranteed operation of 74AUP1G79GV,125?

The device is fully specified from 0.8 V to 3.6 V per JEDEC JESD8-12. At 0.8 V, propagation delay is 19.7 ns (CL = 5 pF), setup time is 3.4 ns, and ICC remains ≤ 0.5 μA-enabling use with thin-film batteries and energy-harvesting sources that output below 1.0 V.

Does 74AUP1G79GV,125 support hot-swap or partial power-down configurations?

Yes. Its IOFF circuitry disables outputs when VCC = 0 V, limiting backflow current to ±0.75 μA maximum. This allows safe insertion/removal in live backplanes and enables selective shutdown of peripheral logic blocks while main system rails remain active.

How does the Schmitt-trigger input improve system robustness?

Schmitt-trigger action provides input hysteresis (≥0.3 V at 1.2 V), allowing reliable operation with slow-rising signals (e.g., RC-based resets or mechanical switch inputs) without external filtering. It suppresses multiple transitions caused by noise near logic thresholds, eliminating metastability in asynchronous control paths.

Can 74AUP1G79GV,125 drive standard CMOS loads directly?

Yes. At VCC = 3.0 V, it delivers VOH ≥ 2.30 V and VOL ≤ 0.50 V while sinking or sourcing 4.0 mA-meeting 74LVC logic thresholds. With 1.8 V supply, it drives 1.9 mA loads while maintaining VIH/VIL margins, supporting direct connection to FPGA I/O banks and microcontroller GPIOs.