Nexperia USA Inc. 74AUP1G80GM,132

Overview

74AUP1G80GM,132 from Nexperia is a single positive-edge-triggered D-type flip-flop in XSON6 (SOT886) package, operating from 0.8 V to 3.6 V supply. It stores data on LOW-to-HIGH clock transitions with guaranteed setup/hold timing, features Schmitt-trigger inputs for noise immunity, and supports partial power-down via IOFF circuitry. It is used in low-power clock-domain synchronization and signal edge alignment in battery-powered IoT sensor nodes.

For engineers reviewing the 74AUP1G80GM,132 datasheet, 74AUP1G80GM,132 pinout, 74AUP1G80GM,132 application, or 74AUP1G80GM,132 equivalent, key selection criteria include ultra-low ICC (≤1.4 μA at −40 °C to +125 °C), IOFF-enabled isolation during power sequencing, VCC range flexibility across 0.8–3.6 V, and validated operation up to 510 MHz at 3.0–3.6 V with 5 pF load.

Technical Context

This device implements a synchronous edge-triggered storage element with transparent input logic preceding a master-slave latch structure. Its Schmitt-trigger inputs provide hysteresis (typ. 0.3 V at VCC = 3.3 V), enabling robust operation with slow-rising control signals. The IOFF circuit actively disables outputs when VCC = 0 V, preventing back-current flow in multi-rail systems.

It operates across three temperature grades (−40 °C to +125 °C), with static and dynamic parameters fully characterized per JEDEC standards JESD8-12 through JESD8C. Propagation delay (tpd) ranges from 1.0 ns (VCC = 3.0–3.6 V, CL = 5 pF) to 38.8 ns (VCC = 0.8 V, CL = 30 pF), and maximum clock frequency drops from 510 MHz to 28 MHz across voltage and load conditions.

Key Specifications

Pinout & Package

XSON6 plastic extremely thin small outline package (SOT886); no leads; 6 terminals; body dimensions 1.0 mm × 1.45 mm × 0.5 mm; wettable flank terminations; thermal pad optional.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar D-type flip-flop applications.

Compared with SN74LVC1G80DBVR and 74LVC1G74GW,125, the 74AUP1G80GM,132 uniquely combines sub-μA static current, IOFF-enabled rail independence, and Schmitt-triggered inputs - making it the sole option for ultra-low-power, multi-rail, noise-prone edge-capture applications.

Availability

74AUP1G80GM,132 is available at Aetrix Electronics and suitable for industrial sensor interface, automotive body control module, portable medical monitor, and low-power wireless node applications requiring stable component supply across extended temperature and voltage ranges.

Supply support for 74AUP1G80GM,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency-enhancing components, with leadership in logic, discrete, and MOSFET technologies serving automotive, industrial, and consumer markets.

The 74AUP (Advanced Ultra-low Power) product line delivers sub-microwatt logic ICs optimized for battery-operated and energy-sensitive systems, emphasizing wide VCC range, rail-to-rail compatibility, and robust power sequencing behavior.

FAQ

What is the minimum recommended VCC for reliable operation at −40 °C?

The datasheet specifies guaranteed operation down to 0.8 V across −40 °C to +125 °C. At −40 °C, VIH remains ≥0.75 × VCC and VOL ≤ 0.50 V at 4 mA load, confirming functional margin even at the 0.8 V lower limit. No derating is required below 0.8 V.

Does the n.c. pin on SOT886 require PCB routing or thermal relief?

No. Pin 5 is internally unconnected and electrically isolated. It requires no trace, solder mask opening, or thermal relief. Standard SOT886 footprint guidelines apply - maintain 0.2 mm clearance to adjacent copper and avoid solder bridging during reflow.

Can the 74AUP1G80GM,132 drive a 50 pF capacitive load reliably?

While not characterized beyond 30 pF in the datasheet, measured tpd increases linearly with load capacitance. At VCC = 3.3 V and CL = 30 pF, tpd = 8.3 ns. Extrapolating, CL = 50 pF yields ~12 ns tpd - still within timing budgets for most 100 MHz designs. For production use above 30 pF, validate setup/hold margins with actual board parasitics.

How does IOFF behave when VCC ramps from 0 V to nominal?

IOFF activates when VCC falls below ~0.2 V and remains active until VCC exceeds ~0.4 V. During this transition, output leakage is limited to ±0.75 μA max. This window ensures clean disable/enable without glitches, supporting controlled power-rail sequencing in multi-supply systems.