Nexperia USA Inc. 74AUP1G80GW,125

Overview

74AUP1G80GW,125 from Nexperia is a single positive-edge-triggered D-type flip-flop in TSSOP5 package, operating from 0.8 V to 3.6 V supply, with 1.4 μA max ICC at −40 °C to +125 °C, 0.5 ns min set-up time at 3.3 V, and Schmitt-trigger inputs for noise immunity. It serves as a level-sensitive storage element in low-power clock domain synchronization and signal edge alignment circuits.

For engineers reviewing the 74AUP1G80GW,125 datasheet, 74AUP1G80GW,125 pinout, 74AUP1G80GW,125 application, or 74AUP1G80GW,125 equivalent, key selection criteria include ultra-low static current, IOFF-enabled partial power-down capability, guaranteed timing across extended temperature range, and compatibility with mixed-voltage I/O systems down to 0.8 V.

Technical Context

This device implements a synchronous edge-triggered storage cell with asynchronous reset-free operation, where data at the D input is latched on the LOW-to-HIGH transition of CP. Its Schmitt-trigger inputs tolerate slow-rising signals and reject noise below hysteresis thresholds (typ. 0.3×VCC to 0.7×VCC).

The IOFF circuit actively disables outputs when VCC = 0 V, blocking backflow current up to ±0.75 μA, enabling safe hot-insertion and multi-rail power sequencing. Propagation delay ranges from 1.0 ns (VCC = 3.3 V, CL = 5 pF) to 38.8 ns (VCC = 0.8 V, CL = 30 pF), supporting clock frequencies up to 510 MHz at 3.3 V.

Key Specifications

Pinout & Package

TSSOP5 (SOT353-1) package: plastic thin shrink small outline, 5-lead, 1.25 mm body width, 0.65 mm lead pitch, exposed pad not present.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar D-type flip-flop applications.

Compared with SN74LVC1G80DBVR and 74LVC1G74GW,125, the 74AUP1G80GW,125 uniquely combines 0.8 V operation, IOFF, and Schmitt inputs-making it the sole option for ultra-low-voltage, hot-pluggable, and EMI-prone applications.

Availability

74AUP1G80GW,125 is available at Aetrix Electronics and suitable for industrial sensor interfaces, automotive body control modules, portable medical wearables, and IoT edge nodes requiring stable component supply across extended temperature and voltage ranges.

Supply support for 74AUP1G80GW,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable, and efficient logic, analog, and discrete components for automotive, industrial, and consumer markets.

The 74AUP (Advanced Ultra-low Power) product line targets battery-constrained and thermally sensitive applications requiring sub-μA static current, wide VCC scalability, and robust ESD tolerance without sacrificing speed.

FAQ

What is the minimum recommended VCC for reliable operation of 74AUP1G80GW,125?

The absolute minimum VCC is 0.8 V per datasheet Section 9. Below this, timing parameters and noise margins are not guaranteed. At 0.8 V, t_pd increases to 20.9 ns (CL = 5 pF), and f_max drops to 50 MHz. For stable 100+ MHz operation, VCC ≥ 1.4 V is recommended.

Does 74AUP1G80GW,125 require external pull-up or pull-down resistors on unused pins?

No. Pin 5 is VCC and must be connected; pin 3 is GND and must be connected; pins 1 (D), 2 (CP), and 4 (Q) are active I/O. There is no NC (no-connect) pin in the TSSOP5 variant-unlike XSON6 versions which include a dedicated n.c. terminal. All five pins serve defined functions.

How does the IOFF feature behave during power sequencing?

When VCC falls below ~0.2 V, the IOFF circuit disables both Q output and internal logic path, limiting leakage to ±0.75 μA regardless of D or CP voltage. This prevents back-current from powered downstream logic into the unpowered flip-flop, satisfying IEC 61000-4-2 system-level ESD robustness requirements.

Can 74AUP1G80GW,125 drive a 50 pF load reliably?

Yes, but with timing impact: at VCC = 3.3 V and CL = 50 pF, t_pd increases to ~7.5 ns (extrapolated from 30 pF data), and f_max drops to ~190 MHz. Output drive strength remains compliant (VOH ≥ 2.3 V, VOL ≤ 0.5 V at 4 mA), but layout should minimize trace capacitance to preserve sub-ns margins.