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Nexperia USA Inc. 74AUP1G86GM,132
- Part No.:
- 74AUP1G86GM,132
- Manufacturer:
- Nexperia USA Inc.
- Category:
- Gates and Inverters
- Package:
- 6-XFDFN
- Datasheet:
-
74AUP1G86GM,132.pdf
- Description:
- IC GATE XOR 1CH 2-INP 6XSON
- Quantity:
- Payment:
- Shipping:
Inventory:4,569
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Product details
Overview
74AUP1G86GM,132 from Nexperia is a single 2-input EXCLUSIVE-OR gate in XSON6 package (SOT886), operating from 0.8 V to 3.6 V supply, featuring Schmitt-trigger inputs for noise immunity, IOFF partial power-down protection, and guaranteed operation from –40 °C to +125 °C. It delivers ultra-low static current (≤1.4 μA max) and propagation delay as low as 0.9 ns at 3.6 V with 5 pF load, enabling use in battery-powered sensor interfaces and level-shifting logic paths.
For engineers reviewing the 74AUP1G86GM,132 datasheet, 74AUP1G86GM,132 pinout, 74AUP1G86GM,132 application, or 74AUP1G86GM,132 equivalent, this device serves as a low-voltage, low-power XOR gate where input rise/fall time tolerance, rail-to-rail compatibility, and power-down isolation are critical - especially in portable IoT nodes, wearables, and multi-rail MCU peripheral interfacing.
Technical Context
This device implements standard XOR logic (Y = A ⊕ B) with Schmitt-trigger inputs that accept slow-rising signals while maintaining clean output transitions. Its IOFF circuit actively disables outputs during VCC = 0 V, preventing backfeed current in partial-power-down systems.
Designed for ultra-low-power operation across wide voltage rails, it meets JEDEC standards JESD8-12 through JESD8-B and supports dynamic loading up to 30 pF with propagation delays specified down to 0.9 ns (VCC = 3.0–3.6 V, CL = 5 pF, Tamb = –40 to +125 °C).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 0.8 V to 3.6 V - Enables direct interface with 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains without level shifters. |
| Max ICC (Static) | 1.4 μA at –40 °C to +125 °C - Ensures negligible quiescent drain in always-on sensor wake-up circuits. |
| tpd (A/B → Y) | 0.9 ns min / 5.2 ns max (VCC = 3.0–3.6 V, CL = 5 pF, –40 to +125 °C) - Supports >100 MHz toggle rates in low-load configurations. |
| IOFF Leakage | ±0.75 μA max (VI/VO = 0–3.6 V, VCC = 0 V) - Prevents cross-talk and bus contention when upstream/downstream sections are powered off. |
| Input Thresholds | VIL ≤ 0.30×VCC, VIH ≥ 0.70×VCC (at +125 °C) - Provides robust noise margin (>30% of VCC) under worst-case thermal conditions. |
| ESD Rating | HBM >5000 V, CDM >1000 V - Sustains handling and board-level ESD events without functional degradation. |
Pinout & Package
XSON6 plastic extremely thin small outline package (SOT886); no leads; 6 terminals; body dimensions 1.0 × 1.45 × 0.5 mm; wettable flank terminals; pin 1 index located on lower-left corner below marking code.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (A) | Data Input | Primary XOR operand input with Schmitt-trigger threshold; tolerant of slow edges and undershoot/overshoot <10% VCC. |
| 2 (B) | Data Input | Secondary XOR operand input; electrically identical to Pin 1; enables bidirectional signal arbitration or parity generation. |
| 3 (GND) | Ground Reference | 0 V reference for all I/O and internal logic; must be low-impedance to maintain noise immunity and IOFF integrity. |
| 4 (Y) | Data Output | CMOS-compatible XOR result; drives capacitive loads up to 30 pF with controlled edge rates; supports open-drain emulation via external pull-up. |
| 5 (n.c.) | No Connect | Internally unconnected terminal; must remain floating - not tied to GND, VCC, or signal lines. |
| 6 (VCC) | Supply Voltage | Power rail input; decoupling capacitor (100 nF) recommended within 2 mm; IOFF activation occurs automatically when VCC = 0 V. |
Key Features
| Feature | Design Value |
|---|---|
| Schmitt-trigger inputs | Enables reliable switching with slow or noisy signals (e.g., mechanical switch debouncing, analog comparator outputs) without external hysteresis components. |
| IOFF partial power-down | Prevents damaging back-current flow when VCC = 0 V while inputs/outputs remain biased - essential for hot-swap and multi-domain power sequencing. |
| Wide VCC range (0.8–3.6 V) | Eliminates need for voltage translators between legacy 1.2 V ASICs, modern 1.8 V FPGAs, and 3.3 V microcontrollers in mixed-supply systems. |
| Ultra-low ICC (≤1.4 μA) | Extends battery life in always-on wake-up logic (e.g., motion-triggered BLE beacon enable) without sacrificing speed or noise immunity. |
| –40 °C to +125 °C operation | Validated for under-hood automotive modules, industrial motor controllers, and outdoor wireless sensor enclosures without derating. |
Applications
| Industrial Sensor Interface | Wearable Motion Detection |
|---|---|
|
Use Scenario: Detecting differential motion signals from dual-axis MEMS accelerometers with asynchronous sampling clocks. IC Role / Device Role / Timing Role: XOR gate compares sign bits of two accelerometer channels to generate zero-crossing pulses indicating directional change. Use Value: Schmitt-trigger inputs reject high-frequency noise from motor vibration; IOFF prevents current leakage when host MCU sleeps. |
Use Scenario: Enabling ultra-low-power step counting by combining quadrature encoder outputs from optical heart-rate sensors. IC Role / Device Role / Timing Role: Generates XOR output used as clock enable for counter logic only when motion is detected - reducing average system current. Use Value: 0.8 V operation allows direct connection to coin-cell–powered analog front-end; 1.4 μA ICC extends battery life beyond 1 year. |
| Multi-Rail MCU Peripheral Arbitration | Low-Voltage Logic-Level Translation |
|
Use Scenario: Resolving bus contention between two 1.8 V I²C masters sharing a 3.3 V pull-up domain. IC Role / Device Role / Timing Role: XOR-based handshake generator ensures only one master asserts SDA at a time, avoiding voltage conflict. Use Value: Bidirectional input tolerance (3.6 V max) permits safe connection to 3.3 V bus; IOFF isolates masters during reset sequences. |
Use Scenario: Converting 1.2 V GPIO toggles from an AI accelerator core into 2.5 V control signals for a display driver IC. IC Role / Device Role / Timing Role: Configured as inverter (A tied to VCC or GND) to shift logic levels while preserving timing integrity. Use Value: Propagation delay variation <0.5 ns across 0.8–3.6 V ensures deterministic setup/hold margins in timing-critical control paths. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar XOR gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G86DBVR | Wider VCC range (1.65–5.5 V); higher ICC (max 10 μA); no IOFF; no Schmitt inputs. | Requires external hysteresis for noisy inputs; unsuitable for partial power-down systems. | Select when interfacing 5 V peripherals and noise immunity is provided externally. |
| 74LVC1G86GW,125 | TSSOP5 package (SOT353-1); same electrical specs but larger footprint (2.2 × 1.35 mm vs. 1.45 × 1.0 mm); no wettable flanks. | Less suitable for automated optical inspection (AOI) and fine-pitch reflow in space-constrained wearables. | Select when board assembly uses legacy TSSOP tooling and thermal performance is less critical than size. |
Compared with SN74LVC1G86DBVR and 74LVC1G86GW,125, the 74AUP1G86GM,132 uniquely combines sub-1 μA static current, Schmitt-trigger inputs, and IOFF in a 1.45 mm × 1.0 mm XSON6 package - making it optimal for miniaturized, battery-sensitive, and multi-power-domain designs where signal integrity and power sequencing are co-constrained.
Availability
74AUP1G86GM,132 is available at Aetrix Electronics and suitable for industrial sensor interfaces, wearable motion detection, multi-rail MCU peripheral arbitration, and low-voltage logic-level translation requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74AUP1G86GM,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance, reliable, and energy-efficient logic, analog, and discrete components for automotive, industrial, and consumer markets.
The 74AUP (Advanced Ultra-low Power) product line targets ultra-low-power logic applications demanding sub-1 μA static current, wide VCC flexibility, and robust operation across –40 °C to +125 °C - specifically engineered for battery-powered and thermally constrained systems.
FAQ
Can 74AUP1G86GM,132 operate reliably at 0.85 V supply?
Yes. The device is fully characterized and guaranteed from 0.8 V to 3.6 V. At 0.85 V, VIH is specified as ≥0.70 × VCC (≥0.595 V) and VOL ≤0.11 V with 20 μA load, ensuring noise margin and logic-level compatibility in ultra-low-voltage subsystems such as energy-harvesting sensor nodes.
What is the function of the n.c. pin (Pin 5) in SOT886?
Pin 5 is internally unconnected and must remain floating - not tied to GND, VCC, or any signal. It is a structural terminal required for mechanical stability and thermal dissipation in the XSON6 package; connecting it risks parasitic coupling or solder bridging during reflow.
How does IOFF behave when VCC ramps from 0 V to nominal?
IOFF activates automatically when VCC drops below ~0.2 V and remains active until VCC exceeds ~0.4 V. During ramp-up, outputs stay disabled until VCC reaches valid logic thresholds; no glitch or metastability occurs, ensuring clean power sequencing in multi-rail systems.
Is the 74AUP1G86GM,132 compatible with lead-free reflow profiles?
Yes. The SOT886 (XSON6) package is qualified for standard IPC/JEDEC J-STD-020 moisture sensitivity level 1 (MSL1) and withstands peak reflow temperatures up to 260 °C. Its wettable flank design supports automated optical inspection (AOI) and ensures reliable solder joint formation.
74AUP1G86GM,132 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AUP
- Package/Case:
- 6-XFDFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- XOR (Exclusive OR)
- Number of Circuits:
- 1
- Number of Inputs:
- 2
- Features:
- -
- Voltage - Supply:
- 0.8V ~ 3.6V
- Current - Quiescent (Max):
- 500 nA
- Current - Output High, Low:
- 4mA, 4mA
- Input Logic Level - Low:
- 0.7V ~ 0.9V
- Input Logic Level - High:
- 1.6V ~ 2V
- Max Propagation Delay @ V, Max CL:
- 7.1ns @ 3.3V, 30pF
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-XSON, SOT886 (1.45x1)
74AUP1G86GM,132 FAQ
1.How can I place an order for 74AUP1G86GM,132 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP1G86GM,132 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP1G86GM,132 reliable?
The price and inventory of 74AUP1G86GM,132 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1G86GM,132 is usually 5 days.
3.What payment methods are accepted for 74AUP1G86GM,132?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP1G86GM,132 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74AUP1G86GM,132?
74AUP1G86GM,132 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP1G86GM,132 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP1G86GM,132?
For technical support, including 74AUP1G86GM,132 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1G86GM,132 requirements.
6.How does Aetrix verify that 74AUP1G86GM,132 is sourced from the original manufacturer or authorized distributors?
All 74AUP1G86GM,132 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1G86GM,132 meets industry standards.
7.What is the process for return or replacement of 74AUP1G86GM,132?
All 74AUP1G86GM,132 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1G86GM,132, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP1G86GM,132 part is unused and in its original packaging.
Return procedure for 74AUP1G86GM,132:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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