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Nexperia USA Inc. 74AUP1G86GW,125
- Part No.:
- 74AUP1G86GW,125
- Manufacturer:
- Nexperia USA Inc.
- Category:
- Gates and Inverters
- Package:
- 5-TSSOP, SC-70-5, SOT-353
- Datasheet:
-
74AUP1G86GW,125.pdf
- Description:
- IC GATE XOR 1CH 2-INP 5TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:14,393
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Product details
Overview
74AUP1G86GW,125 from Nexperia is a single 2-input EXCLUSIVE-OR gate with Schmitt-trigger inputs, operating across 0.8 V to 3.6 V supply, delivering 0.9 μA max ICC at 25 °C, 4.0 ns max propagation delay at 3.6 V/CL = 5 pF, and IOFF-enabled partial power-down protection. It serves in low-power logic interfacing, signal conditioning, and bus arbitration circuits in battery-powered IoT sensors and portable medical monitors.
For engineers reviewing the 74AUP1G86GW,125 datasheet, 74AUP1G86GW,125 pinout, 74AUP1G86GW,125 application, or 74AUP1G86GW,125 equivalent, this device offers verified Schmitt-trigger noise immunity, sub-1 μA static current, -40 °C to +125 °C operation, and TSSOP5 package compatibility for space-constrained PCB layouts requiring robust XOR functionality at ultra-low voltage.
Technical Context
This device implements a single 2-input XOR function with hysteresis on both inputs (typical ΔV = 0.3 V), enabling reliable switching under slow-rising or noisy signals. Its CMOS AUP (Advanced Ultra-low Power) process ensures rail-to-rail input tolerance up to 3.6 V independent of VCC, and supports mixed-voltage domain interfacing.
The IOFF circuit actively disables outputs when VCC = 0 V, limiting backflow current to ±0.75 μA max over -40 °C to +125 °C, making it suitable for hot-swap and partial-power-down systems where upstream/downstream logic may remain active during local power gating.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 0.8 V to 3.6 V - Enables direct interface with 0.9 V, 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains without level shifters. |
| ICC (max) | 0.9 μA at 25 °C - Ensures <1 μW static power at 1.8 V, critical for multi-year battery life in always-on sensor nodes. |
| tpd (max) | 4.0 ns at VCC = 3.6 V, CL = 5 pF - Supports >100 MHz toggle rates in low-capacitance signal paths like clock enable gating. |
| VIH/VIL Hysteresis | Typical 0.3 V - Rejects noise spikes ≤300 mV on input lines, eliminating need for external RC filtering in industrial control I/O. |
| IOFF Leakage | ±0.75 μA max at VCC = 0 V - Prevents >100 μA backfeed into powered-down sections, satisfying IEC 61000-4-2 system-level ESD robustness requirements. |
| Operating Temp | -40 °C to +125 °C - Qualified for under-hood automotive modules, industrial PLC I/O cards, and high-reliability edge compute units. |
Pinout & Package
TSSOP5 (SOT353-1) package: plastic thin shrink small outline, 5-lead, 1.25 mm body width, 0.65 mm lead pitch, 0.95 mm height - optimized for automated optical inspection and reflow soldering in high-density consumer electronics.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (B) | Data Input | Schmitt-triggered input accepting 0–3.6 V regardless of VCC; enables direct connection to higher-voltage GPIOs or analog comparators. |
| 2 (A) | Data Input | Second Schmitt-triggered input; XOR output Y = A ⊕ B; both inputs support identical voltage and timing specs. |
| 3 (GND) | Ground Reference | 0 V reference for all internal logic and IOFF circuitry; must be connected before VCC to avoid latch-up risk per JESD78 Class II B. |
| 4 (Y) | Data Output | Push-pull CMOS output driving loads up to ±4 mA at 3.0 V; supports fan-out of ≥10 to same-family AUP gates. |
| 5 (VCC) | Supply Voltage | Primary power rail; IOFF activation occurs automatically when VCC drops below ~0.2 V, disabling Y without external control. |
Key Features
| Feature | Design Value |
|---|---|
| Schmitt-trigger inputs | Guarantees clean transitions on slow or noisy signals (e.g., mechanical switch debouncing, thermistor ADC references) without external hysteresis components. |
| IOFF partial power-down | Eliminates backflow current during VCC ramp-down, enabling safe insertion/removal in modular systems and reducing system-level standby power by >50 %. |
| Overvoltage-tolerant inputs | Accepts 0–3.6 V inputs even when VCC = 0.8 V, allowing interoperability with legacy 3.3 V peripherals while powered from 1.2 V rails. |
| Low dynamic noise | Overshoot/undershoot <10 % of VCC minimizes crosstalk in adjacent high-speed traces, supporting placement near RF sections in wearable transceivers. |
| JESD78 latch-up immunity | Exceeds 100 mA - ensures robustness against transient ground bounce or ESD-induced latch-up in ungrounded test fixtures or field-deployed equipment. |
Applications
| Industrial Sensor Interface | Portable Medical Monitor |
|---|---|
|
Use Scenario: Level-shifting and noise filtering between a 3.3 V microcontroller GPIO and a 1.8 V MEMS accelerometer with slow-rising interrupt signals. IC Role / Device Role / Timing Role: XOR gate configured as controlled inverter (A = fixed logic, B = sensor INT#) with Schmitt-trigger input rejecting EMI from motor drivers. Use Value: Eliminates external RC filter and level shifter, reducing BOM count by 3 components and PCB area by 2.5 mm² while maintaining <100 ns response time. |
Use Scenario: Pulse-width modulation (PWM) signal conditioning for LED backlight dimming in a handheld ECG device powered by coin-cell battery. IC Role / Device Role / Timing Role: XOR used as edge detector (A = PWM, B = delayed PWM) generating precise strobe pulses synchronized to display refresh cycles. Use Value: Achieves 0.9 μA quiescent current contribution, extending battery life to 18 months at 10% duty cycle, versus 4.2 μA for standard LVC-series alternatives. |
| Automotive Body Control Module | IoT Edge Node Security |
|
Use Scenario: Redundant door-lock status validation using two independent Hall-effect sensors feeding XOR to detect mismatch indicating sensor fault or tampering. IC Role / Device Role / Timing Role: Fault-detection logic element operating at 5 V tolerant inputs while powered from 3.3 V MCU rail, leveraging IOFF during sleep mode. Use Value: Provides fail-safe diagnostic capability with no additional power overhead during 95% low-power sleep period, meeting ISO 16750-2 pulse test requirements. |
Use Scenario: Hardware-based one-time password (OTP) generation seed XOR-mixing in a BLE-connected smart lock, where entropy sources require deterministic combination. IC Role / Device Role / Timing Role: Low-power combinational logic block performing real-time bit-wise XOR of TRNG output and stored key fragment at 1 MHz clock rate. Use Value: Delivers <4 ns propagation delay at 1.8 V with <1 μA ICC, ensuring cryptographic latency remains below 5 ns while consuming <0.2 μW static power. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 2-input XOR gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G86DBVR | Wider VCC range (1.65–5.5 V); higher ICC (10 μA typ); no IOFF; no Schmitt inputs. | Requires external hysteresis for noisy environments; unsuitable for partial power-down systems. | Select only if interfacing exclusively with 3.3 V/5 V systems and board space allows RC filtering. |
| 74LVC1G86GV,125 | Same AUP family but in SOT753 (5-lead SC-74A); identical electrical specs; slightly larger footprint (2.1 × 1.25 mm vs. 2.2 × 1.35 mm). | Compatible pinout but requires PCB land pattern revision; thermal resistance 290 K/W vs. 260 K/W for TSSOP5. | Choose for legacy SOT753 assembly lines or where JEDEC-standard SC-74A is mandated. |
Compared with SN74LVC1G86DBVR and 74LVC1G86GV,125, the 74AUP1G86GW,125 uniquely combines sub-1 μA static current, Schmitt-trigger noise immunity, and IOFF protection-enabling true zero-power state retention in energy-harvesting and battery-critical designs where others require supplemental circuitry or compromise on reliability.
Availability
74AUP1G86GW,125 is available at Aetrix Electronics and suitable for industrial sensor interfaces, portable medical monitors, automotive body control modules, and IoT edge node security applications requiring stable component supply across extended temperature ranges and ultra-low power budgets.
Supply support for 74AUP1G86GW,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions with emphasis on reliability, energy efficiency, and miniaturization.
The 74AUP1G86 belongs to Nexperia's Advanced Ultra-low Power (AUP) logic family, designed specifically for battery-operated and energy-sensitive applications demanding sub-microamp static current, wide-VCC operation, and robust noise immunity without external components.
FAQ
Does 74AUP1G86GW,125 support true bidirectional signal routing?
No. The 74AUP1G86GW,125 is a unidirectional XOR gate with defined inputs (A, B) and output (Y). It lacks internal bus-hold or direction-control circuitry. Its IOFF feature only disables the output driver during power-down-it does not enable reverse signal flow or bus transceiver behavior. Bidirectional use requires external isolation or dedicated transceivers.
Can the Schmitt-trigger inputs be disabled to use standard CMOS thresholds?
No. Schmitt-trigger action is inherent to the input structure and cannot be disabled via pins, voltage, or configuration. The hysteresis (typically 0.3 V) is fixed and provides guaranteed noise margin across the full VCC range. For non-hysteresis operation, consider the pin-compatible 74AUP1G00 or 74AUP1G02, though those lack input overvoltage tolerance.
What is the maximum capacitive load the output can drive while maintaining 4 ns tpd?
At VCC = 3.6 V, the 4.0 ns max propagation delay is specified for CL = 5 pF. Driving >10 pF increases tpd to 4.8 ns (max) at 3.6 V. For loads >15 pF, tpd exceeds 5.4 ns. To maintain timing integrity, keep total load (including trace capacitance) ≤5 pF or use a buffer stage for heavier loads.
Is the 74AUP1G86GW,125 compliant with automotive AEC-Q200 stress testing?
No. While qualified for -40 °C to +125 °C operation and meeting JESD78 latch-up and ESD standards (HBM >5 kV, CDM >1 kV), the 74AUP1G86GW,125 is not AEC-Q200 qualified. For automotive applications requiring AEC-Q200, Nexperia offers the automotive-grade variant 74AUP1G86GW-Q100, which undergoes additional temperature cycling and humidity testing.
74AUP1G86GW,125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AUP
- Package/Case:
- 5-TSSOP, SC-70-5, SOT-353
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- XOR (Exclusive OR)
- Number of Circuits:
- 1
- Number of Inputs:
- 2
- Features:
- -
- Voltage - Supply:
- 0.8V ~ 3.6V
- Current - Quiescent (Max):
- 500 nA
- Current - Output High, Low:
- 4mA, 4mA
- Input Logic Level - Low:
- 0.7V ~ 0.9V
- Input Logic Level - High:
- 1.6V ~ 2V
- Max Propagation Delay @ V, Max CL:
- 7.1ns @ 3.3V, 30pF
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 5-TSSOP
74AUP1G86GW,125 FAQ
1.How can I place an order for 74AUP1G86GW,125 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP1G86GW,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP1G86GW,125 reliable?
The price and inventory of 74AUP1G86GW,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1G86GW,125 is usually 5 days.
3.What payment methods are accepted for 74AUP1G86GW,125?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP1G86GW,125 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74AUP1G86GW,125?
74AUP1G86GW,125 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP1G86GW,125 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP1G86GW,125?
For technical support, including 74AUP1G86GW,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1G86GW,125 requirements.
6.How does Aetrix verify that 74AUP1G86GW,125 is sourced from the original manufacturer or authorized distributors?
All 74AUP1G86GW,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1G86GW,125 meets industry standards.
7.What is the process for return or replacement of 74AUP1G86GW,125?
All 74AUP1G86GW,125 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1G86GW,125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP1G86GW,125 part is unused and in its original packaging.
Return procedure for 74AUP1G86GW,125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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