Nexperia USA Inc. 74AUP1G885DC,125

Overview

74AUP1G885DC,125 from Nexperia is a low-power dual-function logic gate in VSSOP8 package, implementing Boolean functions 1Y = A × C and 2Y = A × B + A × C with Schmitt-trigger inputs. It operates across 0.8 V to 3.6 V supply, delivers <0.9 µA max ICC at 25 °C, supports -40 °C to +125 °C ambient, and features IOFF for partial power-down in battery-backed systems.

For engineers reviewing the 74AUP1G885DC,125 datasheet, 74AUP1G885DC,125 pinout, 74AUP1G885DC,125 application, or 74AUP1G885DC,125 equivalent, key selection criteria include its dual-output combinational logic capability, ultra-low static current, overvoltage-tolerant 3.6 V inputs, and guaranteed operation down to 0.8 V - critical for multi-rail IoT sensor nodes and portable MCU peripheral interfacing.

Technical Context

This device integrates two independent logic functions in a single 8-pin VSSOP package: one AND gate (1Y = A × C) and one OR-AND sum-of-products gate (2Y = A × B + A × C). All three inputs (A, B, C) feature Schmitt-trigger action, enabling robust noise immunity against slow-rising signals and eliminating external hysteresis components.

Its IOFF circuit actively disables outputs when VCC = 0 V, blocking backflow current up to ±0.75 µA (max at -40 °C to +125 °C), making it suitable for hot-swap and partial-power-down architectures. The design complies with JEDEC standards JESD8-12 through JESD8-B across five voltage ranges and meets HBM ESD >5000 V and CDM >1000 V.

Key Specifications

Pinout & Package

VSSOP8 plastic very thin shrink small outline package (SOT765-1), 8 leads, body width 2.3 mm, pin pitch 0.5 mm, height 0.95 mm - optimized for space-constrained PCB layouts in wearables and compact controllers.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-function logic gate applications.

Compared with 74LVC1G97GW,125 and SN74LVC1G57DBVR, the 74AUP1G885DC,125 uniquely delivers ultra-low ICC (<0.9 µA), guaranteed IOFF, and Schmitt-trigger inputs in an 8-pin VSSOP - making it the only option qualified for extended-temperature, low-power, and partial-power-down use cases.

Availability

74AUP1G885DC,125 is available at Aetrix Electronics and suitable for industrial sensor interfaces, automotive body control modules, portable medical monitors, and smart home hub controllers requiring stable component supply across extended temperature and ultra-low power constraints.

Supply support for 74AUP1G885DC,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance logic, discrete, and MOSFET solutions with focus on efficiency, reliability, and miniaturization for automotive, industrial, and consumer markets.

The 74AUP (Advanced Ultra-low Power) logic family targets battery-powered and energy-sensitive applications where sub-µA quiescent current, wide VCC scalability, and robust IO behavior are mandatory design requirements.

FAQ

What is the maximum allowable input voltage when VCC = 0.8 V?

The 74AUP1G885DC,125 supports input voltages up to 3.6 V regardless of VCC level, per datasheet Table 5 (VI input voltage: −0.5 V to +4.6 V) and Section 2 ("Overvoltage tolerant inputs to 3.6 V"). This allows safe interfacing with higher-voltage signals in mixed-supply systems without external clamping.

Does the IOFF feature activate automatically when VCC drops below a threshold?

Yes - the IOFF circuitry activates when VCC = 0 V, disabling both outputs (1Y and 2Y) and limiting leakage to ±0.75 µA maximum across −40 °C to +125 °C (Table 7, IOFF parameter). No external control signal is required; activation is intrinsic to the power rail state.

Can Pin 5 (n.c.) be tied to GND or VCC for mechanical stability?

No - Pin 5 is internally unconnected and must remain floating per datasheet Table 3 and Figure 1 pinning diagram. Connecting it to GND or VCC introduces parasitic capacitance and potential coupling paths that may degrade noise immunity or timing margins, especially with Schmitt-trigger inputs.

How does propagation delay vary with load capacitance at 1.8 V supply?

At VCC = 1.8 V and CL = 15 pF, tpd is 1.2 ns (min) to 6.9 ns (max) for A→1Y and 1.2 ns to 7.2 ns for A→2Y (Table 8, −40 °C to +125 °C column). Delay increases linearly with CL: e.g., at CL = 30 pF, max delay rises to 10.4 ns for A→2Y, confirming predictable capacitive loading behavior.