Nexperia USA Inc. 74AUP1G885GD,125

Overview

74AUP1G885GD,125 from Nexperia is a low-power dual-function logic gate implementing 1Y = A × C and 2Y = A × B + A × C, with Schmitt-trigger inputs for noise immunity across 0.8 V–3.6 V supply. It features IOFF partial power-down protection, 0.9 µA max ICC, and operates from –40 °C to +125 °C in an XSON8 (SOT996-2) package.

For engineers reviewing the 74AUP1G885GD,125 datasheet, 74AUP1G885GD,125 pinout, 74AUP1G885GD,125 application, or 74AUP1G885GD,125 equivalent, key selection criteria include ultra-low static current, overvoltage-tolerant inputs up to 3.6 V, propagation delay as low as 2.1 ns at 3.0 V, and compatibility with battery-powered IoT sensors and portable medical monitors requiring robust input transition handling.

Technical Context

This device integrates two independent Boolean functions in a single 8-terminal XSON package: one AND gate (1Y = A × C) and one OR-AND sum-of-products gate (2Y = A × B + A × C). All three inputs (A, B, C) feature Schmitt-trigger action, enabling reliable operation with slow-rising signals and high noise margin.

The IOFF circuit actively disables outputs when VCC = 0 V, limiting backflow current to ±0.75 µA, while input clamping supports VI up to 4.6 V regardless of supply state. Static power consumption remains ≤1.4 µA across full temperature range (–40 °C to +125 °C) and supply (0.8 V–3.6 V).

Key Specifications

Pinout & Package

XSON8 (SOT996-2) package: plastic extremely thin small outline, no leads, 8 terminals, body size 1.2 × 1.0 × 0.35 mm, thermal pad exposed on bottom, pin 1 index in lower-left corner below marking code.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-function logic gate applications.

Compared with 74LVC1G97GW,125 and SN74LVC1G98DCKR, the 74AUP1G885GD,125 uniquely delivers simultaneous ultra-low ICC (<1.4 µA), IOFF protection, and Schmitt-trigger noise immunity in a minimal 1.2 × 1.0 mm XSON8 package-making it the sole option for space-constrained, battery-critical, and mixed-voltage industrial edge nodes.

Availability

74AUP1G885GD,125 is available at Aetrix Electronics and suitable for portable medical sensors, automotive body control modules, industrial IoT edge nodes, and wearable health monitors requiring stable component supply across extended temperature and voltage ranges.

Supply support for 74AUP1G885GD,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable logic, discrete, and MOSFET solutions optimized for efficiency, miniaturization, and robustness in high-volume applications.

The 74AUP (Advanced Ultra-low Power) product line targets battery-powered and thermally constrained systems where nanowatt static power, wide VCC flexibility, and guaranteed IOFF behavior are mandatory design requirements.

FAQ

What is the maximum allowable input voltage when VCC = 0 V?

The 74AUP1G885GD,125 supports input voltages from –0.5 V to +4.6 V regardless of VCC state, per Absolute Maximum Ratings Table 5. This allows safe connection to powered peripherals during system power-down without risk of latch-up or damage, provided input current remains within ±50 mA limits.

Does this device support true bidirectional signal routing?

No. The 74AUP1G885GD,125 is a unidirectional logic gate with dedicated inputs (A, B, C) and outputs (1Y, 2Y). It contains no internal bus switches or direction-control circuitry. Signal flow is strictly input → output; reverse current paths are blocked by output stage design and IOFF protection.

Can the n.c. pin be grounded or left floating on the PCB?

The n.c. pin must remain unconnected-neither grounded nor tied to VCC. Per datasheet Section 6.2, it is internally not bonded. Connecting it risks parasitic coupling, increased capacitance on adjacent pins, or mechanical stress on the die attach. Standard practice is to omit any copper or solder mask opening at that location.

How does propagation delay vary with load capacitance?

Propagation delay increases linearly with load capacitance: at VCC = 3.0 V, tpd rises from 2.1 ns (CL = 5 pF) to 4.2 ns (CL = 30 pF) for A→1Y path. Designers must account for this in timing budgets-especially in high-fanout nets-and use the CL = 5 pF value only when driving minimal capacitive loads like another gate's input.