Nexperia USA Inc. 74AUP1G885GF,115

Overview

74AUP1G885GF,115 from Nexperia is a low-power dual-function logic gate implementing Boolean functions 1Y = A × C and 2Y = A × B + A × C in a single 8-terminal XSON package. It operates across 0.8 V to 3.6 V supply, features Schmitt-trigger inputs for noise immunity, IOFF circuitry for partial power-down protection, and is rated for -40 °C to +125 °C. It serves as a compact combinational logic block in battery-powered sensor interfaces and portable MCU peripheral control.

For engineers reviewing the 74AUP1G885GF,115 datasheet, 74AUP1G885GF,115 pinout, 74AUP1G885GF,115 application, or 74AUP1G885GF,115 equivalent, key selection criteria include its dual-output logic mapping, sub-1 µA static ICC at 25 °C, IOFF-enabled system-level power sequencing, and compatibility with 1.2 V/1.8 V/3.3 V I/O domains in space-constrained designs.

Technical Context

This device integrates two independent logic functions-AND (1Y) and OR-of-ANDs (2Y)-within a single CMOS gate, eliminating discrete gate stacking. All inputs feature Schmitt-trigger thresholds (VIH/VIL varying with VCC), enabling robust operation with slow-rising signals from mechanical switches or RC networks.

The IOFF circuit actively disables outputs when VCC = 0 V, limiting backflow current to ±0.75 µA max over temperature, making it suitable for hot-swap and multi-rail partial-power-down systems. Propagation delays range from 1.1 ns (VCC = 3.3 V, CL = 5 pF) to 7.9 ns (VCC = 0.8 V, CL = 30 pF), supporting timing-critical signal conditioning in mixed-voltage subsystems.

Key Specifications

Pinout & Package

XSON8 package (SOT1089), 1.2 mm × 1.0 mm × 0.35 mm body, no leads, 8 terminals, wettable flank profile for automated optical inspection.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-function logic gate applications.

Compared with 74LVC1G97GW,125 and SN74AUP1G57DBVR, the 74AUP1G885GF,115 uniquely delivers Schmitt-trigger noise immunity *and* IOFF in the smallest XSON8 variant, making it optimal for high-reliability, low-power, mixed-signal edge nodes requiring deterministic timing and safe power sequencing.

Availability

74AUP1G885GF,115 is available at Aetrix Electronics and suitable for industrial sensor interfaces, portable MCU peripheral control, and automotive body control modules requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74AUP1G885GF,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions optimized for power efficiency and reliability.

The 74AUP (Advanced Ultra-low Power) logic family targets battery-powered and energy-sensitive applications, emphasizing sub-microamp ICC, wide VCC scalability, and robust IO characteristics for next-generation portable and automotive electronics.

FAQ

What is the maximum capacitive load the 74AUP1G885GF,115 can drive while maintaining specified propagation delay?

The device is characterized up to 30 pF load capacitance across all VCC ranges. At VCC = 3.3 V and CL = 30 pF, tpd remains ≤7.3 ns for A→1Y and ≤7.9 ns for A→2Y. Driving loads beyond 30 pF increases delay nonlinearly and may exceed timing budgets in high-speed interfaces - external buffering is recommended above this limit.

Can the n.c. pin be grounded or tied to VCC without affecting operation?

No - the n.c. (pin 5) is internally unconnected and must remain floating. Tying it to GND or VCC introduces parasitic coupling, risks latch-up under ESD stress, and violates Nexperia's recommended handling per datasheet Section 6.2. PCB layout should omit any metal connection to this pad.

How does the IOFF feature behave when VCC ramps from 0 V to nominal voltage?

IOFF activates when VCC drops below ~0.2 V and remains active until VCC exceeds ~0.5 V. During this transition, output leakage is limited to ±0.75 µA max. The output enters high-impedance state within 100 ns of VCC crossing the turn-off threshold, ensuring clean break-before-make behavior in power-rail sequencing.

Is the 74AUP1G885GF,115 compatible with 1.2 V I/O standards such as MIPI I3C or JEDEC JESD8-12?

Yes - it complies fully with JESD8-12 (0.8 V to 1.3 V), supports VIH(min) = 0.70×VCC and VIL(max) = 0.30×VCC at 1.2 V, and delivers VOH(min) = 1.08 V and VOL(max) = 0.12 V at IO = ±1.1 mA. This meets MIPI I3C open-drain and push-pull timing margins when used with appropriate pull resistors.