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Nexperia USA Inc. 74AUP1G885GM,125
- Part No.:
- 74AUP1G885GM,125
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 8-XFQFN Exposed Pad
- Datasheet:
-
74AUP1G885GM,125.pdf
- Description:
- IC GATE DUAL FUNCTION 8-XQFN
- Quantity:
- Payment:
- Shipping:
Inventory:88,000
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Product details
Overview
74AUP1G885GM,125 from Nexperia is a low-power dual-function logic gate implementing Boolean functions 1Y = A × C and 2Y = A × B + A × C, with Schmitt-trigger inputs for noise immunity and IOFF circuitry enabling partial power-down operation. It operates across 0.8 V to 3.6 V supply, delivers <0.9 µA max ICC at 25 °C, supports –40 °C to +125 °C ambient, and is used in battery-powered sensor interface and level-shifting logic blocks.
For engineers reviewing the 74AUP1G885GM,125 datasheet, 74AUP1G885GM,125 pinout, 74AUP1G885GM,125 application, or 74AUP1G885GM,125 equivalent, key selection criteria include its dual-output combinational logic capability, ultra-low static current, IOFF-enabled system-level power gating, and compatibility with sub-1 V digital rails in portable and automotive body electronics.
Technical Context
This device integrates two independent logic functions in a single 8-terminal XSON package (SOT902-2), with inputs A, B, C feeding both outputs: 1Y realizes AND of A and C, while 2Y implements OR of (A AND B) and (A AND C). All inputs feature Schmitt-trigger thresholds for robust signal integrity with slow-rising waveforms.
Its IOFF circuit actively disables outputs when VCC = 0 V, blocking backflow current up to ±0.75 µA, and it complies with JEDEC standards JESD8-12 through JESD8-B across its full 0.8–3.6 V operating range - enabling interoperability in mixed-voltage systems without external level shifters.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 0.8 V to 3.6 V - enables direct interface with 0.9 V, 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains without level translation. |
| Max ICC (Static) | 0.9 µA at –40 °C to +125 °C - ensures negligible battery drain in always-on sensor nodes and wake-up circuits. |
| IOFF Leakage | ±0.75 µA at VCC = 0 V - prevents destructive back-current during hot-swap or partial power-down sequencing in multi-rail systems. |
| Propagation Delay | 1.1 ns (min) to 4.2 ns (max) at VCC = 3.0–3.6 V, CL = 5 pF - supports >200 MHz toggle rates in compact timing-critical paths. |
| Input Thresholds | VIL ≤ 0.3×VCC, VIH ≥ 0.65×VCC (typ.) - provides >30% noise margin at 1.8 V and >55% at 3.3 V under worst-case temperature. |
| ESD Rating | HBM >5000 V, CDM >1000 V - eliminates need for external ESD protection in handheld and industrial I/O interfaces. |
| Operating Temperature | –40 °C to +125 °C - qualified for under-hood automotive, industrial PLC, and outdoor IoT edge node deployment. |
Pinout & Package
XSON8 package (SOT902-2): plastic extremely thin small outline, no leads, 8 terminals, body size 1.35 mm × 1.0 mm × 0.35 mm, thermal pad optional, pin 1 index marked on lower-left corner below marking code "58".
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | A | Primary input controlling both logic outputs; must be HIGH to enable any output activity. |
| 2 | VCC | Single-supply rail; powers internal logic and output drivers; IOFF activates when VCC = 0 V. |
| 3 | B | Secondary input to 2Y only; contributes to OR term (A × B) in 2Y = A×B + A×C. |
| 4 | 1Y | Output of AND function (A × C); driven high only when both A and C are HIGH. |
| 5 | GND | Reference ground for all inputs, outputs, and internal biasing; required for IOFF functionality. |
| 6 | n.c. | No-connect terminal; internally unconnected; must remain floating or tied to GND per layout best practice. |
| 7 | 2Y | Output of sum-of-products function (A×B + A×C); active-HIGH when A is HIGH and either B or C is HIGH. |
| 8 | C | Input shared by both outputs; participates in 1Y = A×C and second term of 2Y = A×B + A×C. |
Key Features
| Feature | Design Value |
|---|---|
| Schmitt-trigger inputs | Enables reliable switching with slow or noisy signals (e.g., mechanical switch debouncing, analog comparator outputs). |
| IOFF partial power-down | Prevents back-current flow when VCC is off, allowing safe insertion/removal in live backplane or modular systems. |
| Overvoltage-tolerant inputs | Accepts up to 3.6 V regardless of VCC setting - supports mixed-voltage interfacing without clamping diodes. |
| Ultra-low dynamic power | CPD = 4.1 pF at 3.3 V enables <1 µW dynamic dissipation at 1 MHz, critical for energy harvesting designs. |
| JEDEC-compliant voltage scaling | Validated across five JEDEC sub-ranges (JESD8-12 to JESD8-B), ensuring interoperability in legacy and next-gen SoC platforms. |
Applications
| Automotive Body Control Module | IoT Sensor Hub Logic |
|---|---|
|
Use Scenario: Combining door lock status (A), window position (B), and rain sensor (C) to drive interior lighting control (1Y) and wiper activation logic (2Y). IC Role / Device Role / Timing Role: Dual-function combinatorial gate performing real-time decision logic without MCU intervention. Use Value: Reduces BOM count by replacing two discrete gates; IOFF allows sleep-mode isolation while retaining sensor wake-up capability. |
Use Scenario: Aggregating motion (A), temperature (C), and humidity (B) sensor alerts into unified interrupt signals for an ultra-low-power microcontroller. IC Role / Device Role / Timing Role: Level-shifting and logic conditioning front-end for 1.2 V/1.8 V sensors interfacing to a 3.3 V host MCU. Use Value: Schmitt-trigger inputs reject EMI from nearby RF modules; sub-1 µA ICC extends coin-cell life beyond 10 years. |
| Industrial PLC Input Conditioning | Portable Medical Device Power Sequencing |
|
Use Scenario: Converting 24 V dry-contact field inputs (via resistive divider) into clean 3.3 V logic levels for PLC FPGA inputs, with debounce and noise rejection. IC Role / Device Role / Timing Role: Input signal conditioner with hysteresis and voltage translation, placed between field wiring and digital controller. Use Value: Eliminates need for external RC filters and Schmitt buffers; overvoltage tolerance simplifies front-end protection design. |
Use Scenario: Enabling sequenced power-up of analog front-end (A), ADC (C), and wireless transceiver (B) based on system reset state and battery health flag. IC Role / Device Role / Timing Role: Low-power state machine building block generating enable signals with precise dependency logic. Use Value: IOFF ensures zero current draw during standby; 0.8 V minimum VCC supports operation directly from buck converter light-load mode. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output combinational logic applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74LVC1G97GW,125 | Higher ICC (max 4 µA), no IOFF, wider VCC (1.65–5.5 V), no Schmitt inputs | Requires external pull-ups for open-drain interfaces; unsuitable for true partial power-down | Select when interfacing to 5 V systems and IOFF is not required |
| SN74AUP1G57DBVR | Same AUP family, identical VCC/ICC/IOFF specs, but implements different logic (A × B + A̅ × C) | Functional mismatch for 1Y = A×C and 2Y = A×B + A×C; requires redesign of truth table mapping | Select only if logic function matches design intent; not drop-in compatible |
Compared with 74LVC1G97GW,125 and SN74AUP1G57DBVR, the 74AUP1G885GM,125 uniquely combines ultra-low ICC, IOFF, Schmitt inputs, and its exact dual-output Boolean function - making it irreplaceable in space-constrained, battery-sensitive, and mixed-voltage power-gated systems.
Availability
74AUP1G885GM,125 is available at Aetrix Electronics and suitable for automotive body electronics, industrial sensor nodes, portable medical devices, and battery-powered IoT gateways requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74AUP1G885GM,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance logic, discrete, and MOSFET solutions optimized for efficiency, reliability, and miniaturization in automotive, industrial, and consumer applications.
The 74AUP (Advanced Ultra-low Power) logic family targets ultra-low-power digital signal conditioning and interface bridging in energy-constrained systems where static current, voltage scalability, and power-state control are critical design parameters.
FAQ
What is the maximum load capacitance supported at 3.3 V supply?
The 74AUP1G885GM,125 is characterized up to 30 pF load capacitance at VCC = 3.0–3.6 V, with tPD increasing from 2.1 ns (CL = 5 pF) to 6.1 ns (CL = 30 pF). Driving >30 pF may exceed recommended output current limits and degrade noise margins; external buffering is advised for heavier loads.
Can pin 6 (n.c.) be connected to GND or left floating?
Pin 6 is internally unconnected and must remain floating per Nexperia's design guidance. Tying it to GND or VCC introduces risk of unintended coupling or leakage paths; PCB layout should omit solder mask opening and avoid routing near this terminal.
Does the IOFF feature work when VCC is ramping or partially powered?
IOFF activates only when VCC = 0 V. During power ramp-up/down, the device operates in normal mode until VCC crosses ~0.2 V, where ΔIOFF leakage rises to ±0.75 µA. For safe hot-swap, ensure VCC transitions fully before asserting inputs or outputs.
How does Schmitt-trigger action improve performance in noisy environments?
Schmitt-trigger inputs provide hysteresis (typically 0.2×VCC), raising the threshold for rising edges and lowering it for falling edges. This rejects noise spikes <200 mV at 1.8 V and prevents multiple toggles on slow or oscillatory signals - essential for switch debouncing and analog comparator outputs.
74AUP1G885GM,125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AUP
- Package/Case:
- 8-XFQFN Exposed Pad
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Logic Type:
- Configurable Multiple Function
- Number of Circuits:
- 1
- Number of Inputs:
- 3
- Schmitt Trigger Input:
- No
- Output Type:
- Single-Ended
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-XQFN (1.6x1.6)
74AUP1G885GM,125 FAQ
1.How can I place an order for 74AUP1G885GM,125 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP1G885GM,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP1G885GM,125 reliable?
The price and inventory of 74AUP1G885GM,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1G885GM,125 is usually 5 days.
3.What payment methods are accepted for 74AUP1G885GM,125?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP1G885GM,125 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74AUP1G885GM,125?
74AUP1G885GM,125 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP1G885GM,125 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP1G885GM,125?
For technical support, including 74AUP1G885GM,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1G885GM,125 requirements.
6.How does Aetrix verify that 74AUP1G885GM,125 is sourced from the original manufacturer or authorized distributors?
All 74AUP1G885GM,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1G885GM,125 meets industry standards.
7.What is the process for return or replacement of 74AUP1G885GM,125?
All 74AUP1G885GM,125 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1G885GM,125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP1G885GM,125 part is unused and in its original packaging.
Return procedure for 74AUP1G885GM,125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74AUP1G885GM,125 Tags
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