Nexperia USA Inc. 74AUP1G885GS,115

Overview

74AUP1G885GS,115 from Nexperia is a low-power dual-function logic gate in XSON8 package (SOT1203), implementing two independent Boolean functions: 1Y = A × C and 2Y = A × B + A × C, with Schmitt-trigger inputs for noise immunity across 0.8 V–3.6 V supply. It delivers ICC ≤ 1.4 µA max at −40 °C to +125 °C and supports partial power-down via IOFF circuitry. Used in battery-powered sensor interfaces and portable I/O expansion.

For engineers reviewing the 74AUP1G885GS,115 datasheet, 74AUP1G885GS,115 pinout, 74AUP1G885GS,115 application, or 74AUP1G885GS,115 equivalent, key selection criteria include ultra-low static current (<1.4 µA), dual-output combinational logic capability, IOFF-enabled power sequencing, and operation down to 0.8 V for energy-constrained embedded systems.

Technical Context

This device integrates two functionally distinct logic outputs on a single die: output 1Y implements a 2-input AND (A·C), while 2Y implements a 3-input OR-AND sum-of-products expression (A·B + A·C). All inputs feature Schmitt-trigger thresholds with hysteresis, enabling robust operation with slow-rising or noisy signals.

Its IOFF circuit actively disables outputs when VCC = 0 V, limiting backflow current to ±0.75 µA max-critical for hot-swap and multi-rail power management. The design complies with JEDEC standards JESD8-12 through JESD8-B and supports full temperature range operation from −40 °C to +125 °C.

Key Specifications

Pinout & Package

XSON8 package (SOT1203): extremely thin, leadless, 1.35 mm × 1.0 mm × 0.35 mm body with 8 terminals; optimized for high-density PCB layouts and automated optical inspection.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-function logic gate applications.

Compared with 74LVC1G97GW,125 and SN74LVC1G57DBVR, the 74AUP1G885GS,115 uniquely combines ultra-low ICC (<1.4 µA), integrated Schmitt triggers, and IOFF-making it the only choice for battery-operated, noise-prone, or multi-rail hot-swap applications requiring guaranteed signal integrity and zero-backflow safety.

Availability

74AUP1G885GS,115 is available at Aetrix Electronics and suitable for industrial sensor interfaces, portable power management systems, automotive body control modules, and low-power PLC inputs requiring stable component supply across extended temperature and voltage ranges.

Supply support for 74AUP1G885GS,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance logic, discrete, and MOSFET solutions with focus on efficiency, reliability, and miniaturization for automotive, industrial, and consumer markets.

The 74AUP (Advanced Ultra-low Power) product line targets energy-sensitive applications demanding sub-microwatt static consumption, wide-VCC operation, and robust signal integrity-designed specifically for battery-powered, always-on, and thermally constrained systems.

FAQ

What is the maximum allowable input voltage when VCC = 0 V?

The 74AUP1G885GS,115 supports overvoltage-tolerant inputs up to 3.6 V regardless of VCC state. When VCC = 0 V, inputs remain safe up to 3.6 V due to internal clamping diodes and IOFF circuitry, preventing damage during hot-insertion or multi-rail sequencing where input signals may be present before power is applied.

Can pin 5 (n.c.) be connected to GND or left floating?

Pin 5 is internally unconnected and must be left floating-no PCB trace, solder mask opening, or metallization should contact it. Connecting it to GND or any other node violates the SOT1203 package specification and risks unintended coupling or thermal stress; Nexperia's layout guidelines explicitly require this terminal to remain unattached.

How does the Schmitt-trigger input improve performance in noisy environments?

Schmitt-trigger inputs provide ~100 mV hysteresis between rising and falling thresholds, eliminating multiple transitions caused by slow edges or noise spikes. This ensures clean, single-shot logic transitions even with input rise/fall times up to 200 ns/V-critical for mechanical switch interfaces, long cable runs, or EMI-heavy industrial settings where standard CMOS inputs would oscillate.

Is the 74AUP1G885GS,115 compatible with 1.2 V FPGA I/O banks?

Yes-the device is fully specified down to 0.8 V supply and meets JESD8-12 (0.8 V–1.3 V) compliance. At VCC = 1.2 V, VIH is guaranteed ≥0.78 V and VIL ≤0.36 V, aligning precisely with LVTTL and LVCMOS 1.2 V FPGA I/O thresholds. Output VOH/VOL also meet drive requirements for 1.2 V logic families under 4 mA load.