Diodes Incorporated 74AUP1G97FZ4-7

Overview

74AUP1G97FZ4-7 from Diodes Incorporated is a single 3-input configurable multiple-function logic gate in X2-DFN1410-6 package, supporting MUX, AND, OR, NAND, NOR, inverter, and buffer functions via input configuration. It operates from 0.8V to 3.6V, delivers ±4mA output drive at 3.0V, features Schmitt-trigger inputs (950mV typical hysteresis at V_CC = 3.0V), and supports IOFF for partial power-down isolation. It is used in battery-powered voltage-level shifting and low-power logic interfacing.

For engineers reviewing the 74AUP1G97FZ4-7 datasheet, 74AUP1G97FZ4-7 pinout, 74AUP1G97FZ4-7 application, or 74AUP1G97FZ4-7 equivalent, key selection criteria include its ultra-low static current (IC < 0.9µA), 3.0V output drive capability, 0.5mm pitch DFN package footprint, Schmitt-trigger noise immunity, and IOFF-enabled mixed-voltage system compatibility.

Technical Context

This device implements a programmable 3-input combinational logic cell where the output Y is determined by all eight possible input combinations of A, B, and C - enabling functional reconfiguration without external components. Its Schmitt-trigger inputs provide defined switching thresholds (e.g., VT+ = 1.88–2.29V, VT− = 0.88–1.24V at 3.0V) and 790–1310mV hysteresis, improving noise margin in slow-rising signal environments.

The IOFF circuit actively disables output leakage during power-down states, preventing backflow current when V_CC = 0V while inputs remain biased at up to 3.6V - critical for hot-swap and multi-rail systems. Its advanced ultra-low-power (AUP) CMOS process ensures CPD = 4.8pF typical and ICC < 1.4µA across −40°C to +125°C.

Key Specifications

Pinout & Package

X2-DFN1410-6 is a 1.4mm × 1.0mm × 0.4mm leadless package with 0.5mm pitch and exposed thermal pad. It supports high-density PCB layouts and offers θ_JA = 430°C/W for thermal management in space-constrained applications.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar configurable logic gate applications.

Compared with SN74LVC1G97DBVR and 74AUP2G00DC,125, the 74AUP1G97FZ4-7 uniquely combines ultra-low-voltage operation (0.8V), Schmitt-trigger noise rejection, and single-device logic configurability - making it irreplaceable in miniaturized, battery-sensitive, and mixed-rail embedded systems.

Availability

74AUP1G97FZ4-7 is available at Aetrix Electronics and suitable for USB-C interface design, wearable sensor hubs, industrial edge nodes, and smart home remote controls requiring stable component supply and long-term lifecycle support.

Supply support for 74AUP1G97FZ4-7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and analog ICs, specializing in high-reliability, low-power, and small-footprint solutions for consumer, industrial, and automotive markets.

The 74AUP logic family targets ultra-low-power portable and battery-operated systems, emphasizing sub-1V operation, nanowatt static consumption, and miniature DFN packaging for space-constrained designs.

FAQ

What logic functions can be implemented using the 74AUP1G97FZ4-7?

The 74AUP1G97FZ4-7 supports eight distinct logic configurations via its three inputs: 2:1 multiplexer, 2-input AND, OR, NAND, NOR (with one or both inputs inverted), inverter, and non-inverting buffer. The function is selected solely by hardwiring A, B, and C to V_CC or GND - no external programming or clock required.

Does the 74AUP1G97FZ4-7 support level shifting between different supply voltages?

Yes - its inputs tolerate up to 3.6V regardless of V_CC, which may be as low as 0.8V. This allows it to accept 3.3V control signals while operating from a 1.2V or 1.8V rail, acting as a passive, unidirectional level shifter without external resistors or direction control.

How does the IOFF feature protect the device during partial power-down?

When V_CC = 0V, the IOFF circuit disables both output FETs, blocking current flow into or out of the Y pin even if inputs remain at 3.6V. This prevents damaging back-current through parasitic diodes and avoids unintended wake-up of downstream circuits - verified per JESD78 latch-up Class I (≥100mA).

Is the X2-DFN1410-6 package compatible with standard reflow profiles?

Yes - the X2-DFN1410-6 package is qualified for IPC/JEDEC J-STD-020 moisture sensitivity level 1 and supports standard lead-free reflow profiles (peak 260°C). Its 0.5mm pitch and exposed thermal pad require controlled solder paste volume and alignment per Diodes' AP02001 pad layout guidelines.