Nexperia USA Inc. 74AUP1G97GF,132

Overview

74AUP1G97GF,132 from Nexperia is a low-power configurable multiple-function logic gate with Schmitt-trigger inputs, supporting MUX, AND, OR, NAND, NOR, inverter, and buffer configurations via its 3-bit input control (A/B/C). It operates across 0.8 V to 3.6 V supply, delivers ≤0.9 μA max ICC at 25 °C, features IOFF for partial power-down protection, and is rated for -40 °C to +125 °C. It enables flexible logic synthesis in space-constrained battery-powered sensor interfaces.

For engineers reviewing the 74AUP1G97GF,132 datasheet, 74AUP1G97GF,132 pinout, 74AUP1G97GF,132 application, or 74AUP1G97GF,132 equivalent, this device offers verified Schmitt-trigger noise immunity, sub-1 μA static current, IOFF-enabled system-level power sequencing, and validated operation down to 0.8 V - critical for ultra-low-voltage IoT node design and mixed-supply level translation.

Technical Context

The 74AUP1G97GF,132 implements a single-output, three-input configurable logic cell using advanced AUP (Advanced Ultra Low Power) CMOS technology. Its Schmitt-trigger inputs provide ≥0.5 V hysteresis at VCC = 3.0 V, enabling robust noise rejection in noisy environments such as industrial control I/O or automotive body electronics.

Function selection is determined by the logic states of inputs A, B, and C per Table 4, with no external configuration pins or registers - all logic modes are combinatorial and fully static. The IOFF circuit actively disables outputs when VCC = 0 V, limiting backflow current to ±0.75 μA maximum over temperature, satisfying JEDEC JESD78 Class II Level B latch-up requirements.

Key Specifications

Pinout & Package

XSON6 plastic extremely thin small outline package (no leads); 6 terminals; body dimensions 1.0 mm × 1.45 mm × 0.5 mm (SOT886).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar configurable logic gate applications.

Compared with SN74LVC1G97DBVR, the 74AUP1G97GF,132 delivers 11× lower static current and guaranteed IOFF protection; versus 74LVC1G98GW,125, it trades enable functionality for minimal footprint and reduced routing complexity in fixed-function deployments.

Availability

74AUP1G97GF,132 is available at Aetrix Electronics and suitable for industrial sensor interfaces, wearable health monitors, automotive body control modules, and smart home hub I/O expansion requiring stable component supply across extended temperature and ultra-low-power operating conditions.

Supply support for 74AUP1G97GF,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a leading semiconductor manufacturer specializing in high-performance, energy-efficient logic, analog, and discrete components for automotive, industrial, and consumer markets.

The 74AUP1G97GF,132 belongs to Nexperia's Advanced Ultra Low Power (AUP) logic family, engineered specifically for battery-operated and thermally constrained applications demanding sub-microamp quiescent current and robust noise immunity.

FAQ

What logic functions can the 74AUP1G97GF,132 implement?

The 74AUP1G97GF,132 supports seven combinational logic functions: 2-input MUX, AND, OR, NAND, NOR, inverter, and buffer. Function selection is determined solely by the logic states of its three inputs (A, B, C) per Table 4 in the datasheet - no configuration registers or external programming is required.

Does the 74AUP1G97GF,132 support level translation between different supply voltages?

Yes - its overvoltage-tolerant inputs accept up to 3.6 V regardless of VCC setting, and its output swing tracks VCC. When VCC = 1.8 V and input = 3.3 V, the Schmitt-trigger input safely clamps excess voltage internally, enabling reliable 3.3 V → 1.8 V level translation without external components.

How does the IOFF feature behave during power-down sequences?

When VCC drops to 0 V, the IOFF circuit forces the Y output into a high-impedance state, limiting leakage current to ±0.75 μA maximum. This prevents back-current flow from powered downstream circuits (e.g., 3.3 V MCU) into the unpowered gate, protecting both devices during staggered power sequencing.

Is the 74AUP1G97GF,132 pin-compatible with other 6-pin logic gates in the AUP family?

No - while it shares the SOT886 (XSON6) package with other AUP single-gate devices, its pin assignment (B-GND-A-Y-VCC-C) is unique to the 74AUP1G97 series. Substituting with 74AUP1G00 or 74AUP1G08 requires PCB redesign due to differing pinouts and functional behavior.