Nexperia USA Inc. 74AUP1G97GM,132

Overview

74AUP1G97GM,132 from Nexperia is a low-power configurable multiple-function logic gate with Schmitt-trigger inputs, supporting MUX, AND, OR, NAND, NOR, inverter, and buffer configurations via its 3-bit input control (A/B/C). It operates across 0.8 V to 3.6 V supply, delivers ≤0.9 μA max ICC at 125 °C, features IOFF for partial power-down protection, and is housed in a 6-terminal XSON6 package (SOT886, 1.0 × 1.45 × 0.5 mm).

For engineers reviewing the 74AUP1G97GM,132 datasheet, 74AUP1G97GM,132 pinout, 74AUP1G97GM,132 application, or 74AUP1G97GM,132 equivalent, this device serves as a space- and power-constrained reconfigurable logic element in battery-powered IoT sensors, portable medical monitors, and ultra-low-power microcontroller peripheral interface conditioning where voltage flexibility and backflow current prevention are critical.

Technical Context

The 74AUP1G97GM implements a single-output combinational logic block whose function is determined by the logic state of its three data inputs (A, B, C), enabling real-time reconfiguration without external programming. Its Schmitt-trigger inputs provide ≥0.5 V hysteresis (e.g., 0.79–1.31 V at VCC = 3.0 V), ensuring robust noise immunity in noisy environments.

IOFF circuitry actively disables the output when VCC = 0 V, limiting power-off leakage to ±0.75 μA and preventing damaging backflow current - a key requirement for hot-swap and multi-rail partial-power-down systems. Propagation delay ranges from 1.5 ns (VCC = 3.0 V, CL = 5 pF) to 22.2 ns (VCC = 1.1 V, CL = 30 pF), scaling predictably with supply and load.

Key Specifications

Pinout & Package

XSON6 plastic extremely thin small outline package (SOT886); no leads; 6 terminals; body dimensions 1.0 mm × 1.45 mm × 0.5 mm; thermal pad optional; pin 1 index located on lower-left corner below marking code.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar configurable logic gate applications.

Compared with SN74LVC1G97DBVR, the 74AUP1G97GM,132 offers 11× lower static current and essential IOFF for power-domain isolation; versus 74AUP1G57GM,132, it adds buffer mode and achieves faster timing - making it optimal for battery-constrained, multi-voltage, or hot-pluggable designs.

Availability

74AUP1G97GM,132 is available at Aetrix Electronics and suitable for IoT sensor nodes, portable medical monitors, and industrial PLC digital input conditioning requiring stable component supply across extended temperature (-40 °C to +125 °C) and ultra-low quiescent current performance.

Supply support for 74AUP1G97GM,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, discrete, and MOSFET solutions, serving automotive, industrial, and consumer markets with JEDEC-compliant, AEC-Q200-qualified components.

The 74AUP (Advanced Ultra Low Power) product line targets battery-powered and energy-sensitive applications, delivering sub-μA static current and wide-VCC operation without sacrificing speed or noise immunity.

FAQ

What logic functions does the 74AUP1G97GM,132 support?

The device supports seven configurable logic functions: 2-input MUX, AND, OR, NAND, NOR, inverter, and buffer. Function selection is determined solely by the logic states of its three inputs (A, B, C) per the documented truth table - no external configuration pins or registers are required.

Can the 74AUP1G97GM,132 operate with VCC = 1.2 V while accepting 3.3 V inputs?

Yes. Its overvoltage-tolerant inputs accept up to 3.6 V regardless of VCC level, and it is fully specified down to 0.8 V. At VCC = 1.2 V, VOH remains ≥0.75 × VCC (≥0.9 V) and VOL ≤0.3 × VCC (≤0.36 V) under load, enabling safe interfacing with higher-voltage peripherals.

How does the IOFF feature protect the circuit during partial power-down?

When VCC = 0 V, the IOFF circuitry disables the output driver and limits both input and output leakage to ±0.75 μA. This prevents reverse current flow from powered downstream circuits (e.g., 3.3 V bus) into the unpowered IC, avoiding latch-up, regulator instability, or unintended activation of connected loads.

Is the 74AUP1G97GM,132 pin-compatible with other 6-pin logic gates in XSON6?

No. While it shares the SOT886 (XSON6) package footprint with other Nexperia logic devices like 74AUP1G00GM, the pin assignment is unique: pins 1–6 map to B/GND/A/Y/VCC/C. Direct substitution requires schematic and layout revision due to differing pinouts and functional behavior.