Nexperia USA Inc. 74AUP1G97GXZ

Overview

74AUP1G97GXZ from Nexperia is a low-power configurable multiple-function logic gate with Schmitt-trigger inputs, supporting MUX, AND, OR, NAND, NOR, inverter, and buffer configurations via its 3-bit input control (A/B/C). It operates across 0.8 V to 3.6 V supply, delivers ≤0.9 μA max ICC at 125 °C, features IOFF for partial power-down protection, and is housed in X2SON6 (SOT1255-2) package with 6 terminals. It targets space-constrained, battery-powered sensor interfaces and level-shifting I/O buffers in industrial IoT edge nodes.

For engineers reviewing the 74AUP1G97GXZ datasheet, 74AUP1G97GXZ pinout, 74AUP1G97GXZ application, or 74AUP1G97GXZ equivalent, this page provides verified functional configuration details, Schmitt-trigger hysteresis values (VH = 0.79–1.31 V at VCC = 3.0 V), IOFF leakage (<±0.75 μA at VCC = 0 V), propagation delay (1.5–5.7 ns depending on VCC and CL), and validated alternative logic gate options for ultra-low-power reconfigurable logic design.

Technical Context

The 74AUP1G97GXZ implements a single-output, three-input configurable logic cell using CMOS architecture with Schmitt-trigger inputs-enabling noise-immune signal conditioning and stable operation under slow-rising or noisy waveforms. Its function selection is determined solely by static logic levels applied to A, B, and C pins, with no internal clock or programming interface required.

All logic functions-including 2-input MUX, inverted AND/NOR/OR variants, inverter, and buffer-are realized through hardwired combinational logic paths within the same silicon die. The IOFF circuit actively disables output drivers when VCC = 0 V, preventing backflow current during partial system power-down, and supports JEDEC-compliant voltage ranges (JESD8-12 to JESD8C).

Key Specifications

Pinout & Package

X2SON6 plastic thermal enhanced extremely thin small outline package (SOT1255-2); 6-terminal, leadless, body size 1.0 × 0.8 × 0.32 mm; exposed thermal pad not electrically connected; pin 1 index located on lower-left corner below marking code.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar configurable logic gate applications.

Compared with SN74LVC1G97DBVR and 74AUP1G57GW,652, the 74AUP1G97GXZ uniquely combines sub-1 μA static current, guaranteed IOFF, and the smallest available X2SON6 footprint-making it the only choice for miniaturized, battery-sensitive designs requiring robust partial power-down behavior.

Availability

74AUP1G97GXZ is available at Aetrix Electronics and suitable for industrial sensor interfaces, low-power wearable input conditioning, multi-voltage level translation, and compact logic reconfiguration requiring stable component supply across extended temperature ranges (−40 °C to +125 °C).

Supply support for 74AUP1G97GXZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions optimized for reliability and energy efficiency.

The 74AUP (Advanced Ultra-low Power) product line is engineered for battery-powered and energy-sensitive applications, emphasizing nanowatt static power, wide supply flexibility, and robust IO characteristics across automotive, industrial, and consumer markets.

FAQ

What logic functions can be implemented with the 74AUP1G97GXZ?

The 74AUP1G97GXZ supports seven distinct logic functions: 2-input MUX, AND, OR, NAND, NOR, inverter, and buffer. Function selection is determined by static HIGH/LOW states applied to its three inputs (A, B, C) per Table 5 in the datasheet-no clock, programming, or external configuration circuitry is required.

Does the 74AUP1G97GXZ require external pull-up or pull-down resistors on its inputs?

No. All inputs (A, B, C) can be directly tied to VCC or GND without external resistors. The device's Schmitt-trigger inputs provide defined thresholds and hysteresis, eliminating floating-state uncertainty and enabling robust logic-level selection via hard-wired connections.

How does the IOFF feature behave during system power sequencing?

When VCC drops to 0 V, the IOFF circuit automatically places the Y output in high-impedance state, blocking current flow from powered downstream circuits (e.g., 3.3 V bus) into the unpowered device. This prevents backfeed damage and ensures clean power-down sequencing in mixed-rail systems.

Can the 74AUP1G97GXZ drive a 15 pF load at 3.0 V while maintaining timing specs?

Yes. At VCC = 3.0 V and CL = 15 pF, the propagation delay is specified as 1.5–5.5 ns (−40 °C to +125 °C), fully meeting timing requirements for sub-100 MHz signal routing. Output drive strength (±4 mA) exceeds typical 15 pF load demands, ensuring monotonic edges without overshoot.