Nexperia USA Inc. 74AUP1G98GM,115

Overview

74AUP1G98GM,115 from Nexperia is a low-power configurable multiple-function logic gate with Schmitt-trigger inputs, supporting MUX, AND, OR, NAND, NOR, inverter, and buffer configurations via its 3-bit input control (A/B/C). It operates across 0.8 V to 3.6 V supply, delivers ≤0.9 μA max ICC at 125 °C, features IOFF for partial power-down protection, and is housed in a 6-terminal XSON6 package (SOT886, 1.0 × 1.45 × 0.5 mm). It is used in space-constrained battery-powered sensor interfaces requiring reconfigurable logic without external components.

For engineers reviewing the 74AUP1G98GM,115 datasheet, 74AUP1G98GM,115 pinout, 74AUP1G98GM,115 application, or 74AUP1G98GM,115 equivalent, this device serves as a single-chip solution for dynamic logic function selection in ultra-low-power embedded control, I²C signal conditioning, and level-shifting interface adaptation - where supply voltage flexibility, ESD robustness (HBM >5 kV), and guaranteed operation down to 0.8 V are critical selection criteria.

Technical Context

The 74AUP1G98 implements a programmable logic cell using three data inputs (A, B, C) to select one of seven combinational functions, with all inputs tolerant to 3.6 V regardless of VCC. Its Schmitt-trigger inputs provide ≥0.07 V hysteresis (up to 1.31 V at 3.0 V), enabling reliable noise immunity in noisy industrial or automotive environments.

IOFF circuitry actively disables outputs during power-down (VCC = 0 V), limiting backflow current to ±0.75 μA, while static power consumption remains ≤1.4 μA across –40 °C to +125 °C. Propagation delay ranges from 1.6 ns (VCC = 3.6 V, CL = 5 pF) to 22.4 ns (VCC = 1.1 V, CL = 30 pF), supporting both high-speed and ultra-low-power timing budgets.

Key Specifications

Pinout & Package

XSON6 plastic extremely thin small outline package (SOT886); no leads; 6 terminals; body dimensions 1.0 mm × 1.45 mm × 0.5 mm; thermal pad optional; pin 1 index located at lower-left corner below marking code "a9".

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar configurable logic gate applications.

Compared with SN74LVC1G98DBVR and 74LVC1G57GW,125, the 74AUP1G98GM,115 uniquely combines sub-1 V operation, IOFF, overvoltage-tolerant inputs, and Schmitt-trigger noise immunity - making it the sole option for ultra-low-power, mixed-rail, and fault-resilient logic reconfiguration.

Availability

74AUP1G98GM,115 is available at Aetrix Electronics and suitable for industrial sensor interfaces, wearable electronics, automotive body control modules, and I²C signal conditioning requiring stable component supply across extended temperature and ultra-low-power constraints.

Supply support for 74AUP1G98GM,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions optimized for power, size, and reliability.

The 74AUP (Advanced Ultra-low Power) logic family targets battery-powered and energy-constrained applications, emphasizing sub-1 V operation, nanoamp quiescent current, and robust signal integrity in compact packages.

FAQ

What logic functions can the 74AUP1G98GM,115 implement?

The device implements seven logic functions-MUX, AND, OR, NAND, NOR, inverter, and buffer-selected by tying its three inputs (A, B, C) to VCC or GND per the function table in Section 7.1. No external programming or clock is needed; configuration is static and determined at power-up.

Does the 74AUP1G98GM,115 require external pull-up or pull-down resistors?

No. All inputs accept direct connection to VCC or GND without external biasing. The Schmitt-trigger inputs have defined thresholds and hysteresis, eliminating floating-input risk and enabling robust logic-level setting with hard rails only.

Can the 74AUP1G98GM,115 be used in a system with mixed supply voltages?

Yes. Inputs tolerate up to 3.6 V regardless of VCC (e.g., 1.8 V supply with 3.3 V input signals), and outputs swing rail-to-rail. This eliminates level shifters in multi-voltage domains such as 1.2 V core + 3.3 V I/O systems.

How does IOFF protect the device during partial power-down?

When VCC = 0 V, the IOFF circuit forces the output (Y) into high-impedance, limiting back-current to ±0.75 μA even if Y is driven externally. This prevents latch-up and damage during power sequencing, hot-swap, or sleep-mode isolation.