Nexperia USA Inc. 74AUP1G98GN,132

Overview

74AUP1G98GN,132 from Nexperia is a low-power configurable multiple-function logic gate with Schmitt-trigger inputs, supporting MUX, AND, OR, NAND, NOR, inverter, and buffer configurations via its 3-bit input control (A/B/C). It operates across 0.8 V to 3.6 V supply, delivers ≤1.4 μA max ICC at −40 °C to +125 °C, and features IOFF circuitry for partial power-down protection. It is used in space-constrained battery-powered sensor interfaces and level-shifting I/O expansion circuits.

For engineers reviewing the 74AUP1G98GN,132 datasheet, 74AUP1G98GN,132 pinout, 74AUP1G98GN,132 application, or 74AUP1G98GN,132 equivalent, key selection criteria include its ultra-low static current, Schmitt-trigger noise immunity, 6-terminal XSON6 (SOT1115) package footprint, and configurable logic behavior without external components.

Technical Context

This device implements a single configurable logic cell using three data inputs (A, B, C) and one output (Y), where the function is determined by the combination of A/B/C states per the defined truth table. Its Schmitt-trigger inputs provide hysteresis (VH = 0.07–1.31 V) for robust noise rejection on slow or noisy signals.

The IOFF circuit enables safe back-drive prevention during partial power-down, while overvoltage-tolerant inputs (up to 3.6 V) allow interfacing across mixed-supply domains. Propagation delay ranges from 1.6 ns (VCC = 3.0–3.6 V, CL = 5 pF) to 22.4 ns (VCC = 1.1–1.3 V, CL = 30 pF), scaling predictably with load and voltage.

Key Specifications

Pinout & Package

XSON6 package (SOT1115): extremely thin small outline, no leads, 6 terminals, body size 0.9 × 1.0 × 0.35 mm, thermal pad optional, pin 1 index located below marking code in lower-left corner.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar configurable logic gate applications.

Compared with 74LVC1G98GW,125 and SN74LVC1G98DBVR, the 74AUP1G98GN,132 uniquely combines ultra-low ICC (<1.4 μA), guaranteed Schmitt-trigger hysteresis, and IOFF in the smallest XSON6 footprint - making it optimal for battery-critical, noise-prone, and multi-rail embedded systems.

Availability

74AUP1G98GN,132 is available at Aetrix Electronics and suitable for industrial sensor interfaces, automotive body control modules, and IoT edge node level-shifting applications requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74AUP1G98GN,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance logic, discrete, and MOSFET solutions optimized for efficiency, reliability, and miniaturization in high-volume electronics.

The 74AUP (Advanced Ultra-low Power) product line targets battery-operated and thermally constrained applications, emphasizing sub-μA static current, wide VCC range, and robust signal integrity - directly addressing demands of wearables, IoT, and automotive subsystems.

FAQ

What logic functions can the 74AUP1G98GN,132 implement?

The 74AUP1G98GN,132 supports seven distinct logic configurations: 2-input MUX with inverted output, 2-input NAND, 2-input NOR with one input inverted, 2-input AND with one input inverted, 2-input NAND with one input inverted, 2-input OR with one input inverted, 2-input NOR, buffer, and inverter. The specific function is selected solely by the logic states applied to its A, B, and C inputs per Table 4 in the datasheet.

Does the 74AUP1G98GN,132 require external pull-up or pull-down resistors on its inputs?

No. All inputs (A, B, C) can be directly tied to VCC or GND without external resistors. The device's input structure supports hard-wired configuration, eliminating BOM cost and board area for discrete biasing components - confirmed in Section 1 (General description) and Table 3 (Pin description).

How does the IOFF feature protect the device during partial power-down?

When VCC = 0 V, the IOFF circuit disables the output driver, limiting leakage current to ±0.75 μA maximum. This prevents reverse current flow from live system buses into the unpowered device, avoiding potential damage or bus contention - a requirement explicitly verified in Table 8 (Static characteristics) under IOFF and ΔIOFF parameters.

Is the 74AUP1G98GN,132 compatible with 1.2 V and 1.8 V supply domains?

Yes. Its 0.8 V to 3.6 V operating range fully covers 1.2 V and 1.8 V logic families. At VCC = 1.2 V, VOH ≥ 1.11 V and VOL ≤ 0.31 V (per Table 8, Tamb = −40 °C to +125 °C); at VCC = 1.8 V, VOH ≥ 1.32 V and VOL ≤ 0.31 V - ensuring reliable HIGH/LOW recognition by standard CMOS receivers.