Nexperia USA Inc. 74AUP1GU04GM,115

Overview

74AUP1GU04GM,115 from Nexperia is a single unbuffered CMOS inverter optimized for ultra-low-power operation across 0.8 V to 3.6 V supply rails, delivering ICC ≤ 0.9 μA (max) at −40 °C to +125 °C, propagation delay as low as 0.3 ns (VCC = 3.6 V, CL = 5 pF), and overvoltage-tolerant inputs up to 3.6 V - deployed in battery-powered sensor nodes and voltage-level translation circuits.

For engineers reviewing the 74AUP1GU04GM,115 datasheet, 74AUP1GU04GM,115 pinout, 74AUP1GU04GM,115 application, or 74AUP1GU04GM,115 equivalent, this device serves as a precision signal inversion element in space-constrained, low-quiescent-current designs requiring rail-to-rail compatibility, high noise immunity (>70% of VCC), and JEDEC-compliant ESD robustness (HBM >5 kV).

Technical Context

The 74AUP1GU04GM implements a single-stage unbuffered inverter topology with no internal gain staging, enabling minimal propagation delay and reduced capacitive loading versus buffered variants. Its IOFF circuitry ensures partial power-down isolation when VCC = 0 V, preventing back-drive current flow between powered and unpowered domains.

Input thresholds scale with VCC (VIH ≥ 0.75×VCC, VIL ≤ 0.25×VCC), supporting consistent logic behavior across its full 0.8–3.6 V operating range. Output drive strength is specified at ±4.0 mA (VCC = 3.0 V), with VOL ≤ 0.50 V and VOH ≥ 2.30 V under worst-case temperature and voltage conditions.

Key Specifications

Pinout & Package

XSON6 plastic extremely thin small outline package (SOT886); 6-terminal, leadless, 1.0 × 1.45 × 0.5 mm body; thermal pad not present; moisture sensitivity level MSL3 per J-STD-020.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar unbuffered inverter applications.

Compared with SN74LVC1G04DBVR and 74LVC1G04GW,125, the 74AUP1GU04GM offers superior sub-1 V operability, lower ICC, and inherent overvoltage tolerance - making it the optimal choice for energy-constrained, multi-rail embedded systems where signal integrity and power efficiency are co-prioritized.

Availability

74AUP1GU04GM,115 is available at Aetrix Electronics and suitable for wireless sensor nodes, medical wearables, industrial I²C interfaces, and low-power crystal oscillator circuits requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74AUP1GU04GM,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, analog, and discrete components for automotive, industrial, and consumer markets.

The 74AUP (Advanced Ultra-low Power) product line targets battery-operated and energy-sensitive applications, emphasizing minimal static/dynamic power, wide voltage scalability, and robust signal integrity in compact packages.

FAQ

Can the 74AUP1GU04GM operate at 0.8 V while driving a 15 pF load?

Yes - the datasheet specifies tpd = 1.4 ns (max) at VCC = 0.8 V and CL = 15 pF across −40 °C to +125 °C. Output drive capability remains functional down to 0.8 V, though VOH drops to ~0.7×VCC and VOL rises to ~0.11×VCC under loaded conditions. This meets standard CMOS threshold requirements for downstream 0.8 V logic.

What is the thermal resistance (RθJA) of the SOT886 package?

The SOT886 (XSON6) package has a typical RθJA of 220 K/W when mounted on a 1 cm² 1-oz copper pad with no thermal vias, per Nexperia's thermal characterization report for AUP-series devices in XSON6. Derating begins at 74 °C ambient, with Ptot decreasing linearly at 3.3 mW/K above that point.

Does the IOFF feature require external biasing or control signals?

No - IOFF activates automatically when VCC = 0 V, regardless of input/output voltage states. No external enable/disable pin or bias network is needed. The internal circuitry blocks current flow between A and Y terminals, limiting II/O leakage to <100 nA even with 3.6 V applied to A or Y while VCC is unpowered.

How does the unbuffered architecture affect noise immunity compared to buffered inverters?

The unbuffered design eliminates internal gain stages, reducing internal node capacitance and susceptibility to supply-induced crosstalk. Measured noise immunity exceeds 70% of VCC across all operating voltages - 15–20% higher than equivalent buffered AUP devices - due to absence of intermediate latch points and simplified signal path.