Nexperia USA Inc. 74AUP1GU04GS,132

Overview

74AUP1GU04GS,132 from Nexperia is a single unbuffered CMOS inverter optimized for ultra-low-power operation across 0.8 V to 3.6 V supply rails, delivering ICC ≤ 0.9 μA (max) at −40 °C to +125 °C, propagation delay as low as 0.3 ns (VCC = 3.6 V, CL = 5 pF), and overvoltage-tolerant inputs up to 3.6 V - deployed in battery-powered sensor nodes and voltage-level translation circuits.

For engineers reviewing the 74AUP1GU04GS,132 datasheet, 74AUP1GU04GS,132 pinout, 74AUP1GU04GS,132 application, or 74AUP1GU04GS,132 equivalent, this device serves as a precision signal inversion element where static power budget, input noise immunity, rail-to-rail compatibility, and compact XSON6 footprint are critical selection criteria.

Technical Context

This unbuffered inverter uses standard CMOS topology with no internal buffering stage, resulting in lower propagation delay and reduced output drive strength compared to buffered variants - enabling precise timing control in oscillator feedback loops and linear amplifier biasing networks.

Its IOFF circuitry enables partial power-down mode during supply sequencing, while overvoltage-tolerant inputs allow safe interfacing with higher-voltage logic domains without external level shifters; JEDEC-compliant voltage standards ensure interoperability across 0.8 V–3.6 V logic families.

Key Specifications

Pinout & Package

XSON6 package (SOT1202): extremely thin small outline, no leads, 6 terminals, body size 1.0 mm × 1.0 mm × 0.35 mm - optimized for space-constrained PCB layouts and automated optical inspection.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar unbuffered inverter applications.

Compared with SN74LVC1G04DBVR and 74LVC1G04GW,125, the 74AUP1GU04GS,132 delivers superior static power efficiency and smaller footprint for space- and energy-constrained designs, though it trades off absolute voltage headroom and package serviceability.

Availability

74AUP1GU04GS,132 is available at Aetrix Electronics and suitable for battery-powered IoT sensors, crystal oscillator modules, and multi-voltage level translation circuits requiring stable component supply across extended temperature ranges.

Supply support for 74AUP1GU04GS,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, analog, and MOSFET solutions for automotive, industrial, and consumer markets.

The 74AUP (Advanced Ultra-low Power) logic family targets ultra-low-power digital signal conditioning in portable and energy-harvesting applications, emphasizing minimal ICC, wide VCC flexibility, and robust ESD performance.

FAQ

Can the 74AUP1GU04GS,132 operate reliably at 0.85 V supply?

Yes - the device is fully specified down to 0.8 V with guaranteed VIH ≥ 0.75 × VCC and VIL ≤ 0.25 × VCC. At 0.85 V, VIH ≥ 0.6375 V and VIL ≤ 0.2125 V are ensured, and propagation delay remains within 6.2 ns (CL = 5 pF) per datasheet Table 8.

Does the 'n.c.' pin require PCB connection or thermal treatment?

No - pins 2 and 4 are internally unconnected and electrically isolated. They must not be soldered to traces, planes, or vias. No thermal pad or copper pour is needed beneath them; standard XSON6 land pattern per SOT1202 drawing suffices.

What is the maximum capacitive load the output can drive without violating timing specs?

The output maintains specified tpd ≤ 2.4 ns (VCC = 3.6 V) up to CL = 5 pF. For CL = 30 pF, tpd increases to ≤ 5.7 ns at VCC = 3.6 V - still functional for <200 MHz clock distribution, but design validation is required for timing-critical paths.

How does IOFF behavior affect system-level power sequencing?

When VCC = 0 V, IOFF disables internal conduction paths, preventing current flow from powered inputs (e.g., 3.3 V GPIO) into the unpowered device. This avoids unintended power injection and ensures clean rail-off states during cold-start or deep-sleep transitions.