Nexperia USA Inc. 74AUP1T02GWH

Overview

74AUP1T02GWH from Nexperia is a single 2-input NOR gate with integrated voltage-level translation, operating from 2.3 V to 3.6 V supply and accepting 1.8 V CMOS inputs. It delivers ultra-low static current (≤1.5 μA), Schmitt-trigger inputs for noise immunity, IOFF partial power-down protection, and operates across –40 °C to +125 °C. It is used in battery-powered IoT sensor nodes requiring level-shifted logic interfacing between 1.8 V controllers and 3.3 V peripherals.

For engineers reviewing the 74AUP1T02GWH datasheet, 74AUP1T02GWH pinout, 74AUP1T02GWH application, or 74AUP1T02GWH equivalent, key selection criteria include its dual-voltage input tolerance (up to 3.6 V), hysteresis-enabled noise rejection (VH ≥ 0.15 V), propagation delay ≤6.6 ns at 3.0 V/15 pF, IOFF leakage ≤±0.75 μA during power-down, and TSSOP5 package compatibility with high-density PCB layouts.

Technical Context

This device implements a single 2-input NOR logic function with Schmitt-trigger inputs enabling robust operation under slow-rising or noisy signal conditions across its full 2.3–3.6 V VCC range. Its IOFF circuit actively disables outputs when VCC = 0 V, preventing backflow current in partial-power-down systems.

The input threshold voltages are dynamically adaptive: VT+ ranges from 0.60 V (2.3 V VCC) to 1.19 V (3.6 V VCC), while VT− shifts from 0.33 V to 0.85 V - delivering ≥0.15 V hysteresis (VH) even at extended temperature (–40 °C to +125 °C), ensuring reliable switching in industrial edge nodes.

Key Specifications

Pinout & Package

TSSOP5 (SOT353-1) package: plastic thin shrink small outline, 5-lead, 1.25 mm body width, 0.65 mm lead pitch, 1.3 mm height - optimized for automated placement and thermal relief in space-constrained PCBs.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 2-input NOR gate with level translation applications.

Compared with SN74LVC1G02DBVR and 74LVC1G02GW, the 74AUP1T02GWH uniquely combines 1.8 V input acceptance, Schmitt-trigger noise immunity, and IOFF power-down isolation in a single TSSOP5 device - making it the only drop-in solution for battery-operated mixed-voltage systems requiring robust signal integrity and zero-power-state safety.

Availability

74AUP1T02GWH is available at Aetrix Electronics and suitable for industrial sensor hubs, wearable health monitors, automotive body control modules, and smart home edge gateways requiring stable component supply across extended temperature and low-power constraints.

Supply support for 74AUP1T02GWH includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, analog, and MOSFET solutions - serving automotive, industrial, and consumer markets with AEC-Q100-qualified and extended-temperature products.

The 74AUP (Advanced Ultra-low Power) product line is engineered for energy-constrained applications demanding nanowatt static power, wide supply range, and robust signal integrity - especially in battery-powered IoT and automotive subsystems.

FAQ

Does 74AUP1T02GWH support true bidirectional level translation?

No. The 74AUP1T02GWH is a unidirectional logic gate: inputs accept 0–3.6 V signals (including 1.8 V), but the output swings only between GND and VCC (2.3–3.6 V). It performs voltage-level translation only from lower-voltage inputs to higher-voltage outputs - not reverse-direction translation. For bidirectional I²C or data bus translation, dedicated translators like NXSA5102 must be used.

What is the maximum capacitive load the 74AUP1T02GWH output can drive reliably?

The output is characterized up to 30 pF load capacitance per dynamic test conditions in the datasheet, with tpd remaining within specification (≤7.5 ns at 2.3 V). Driving >30 pF may increase propagation delay nonlinearly and risk output rise/fall time degradation. For loads exceeding 30 pF, add a series resistor (10–33 Ω) near the driver to dampen ringing and maintain signal integrity without violating VOH/VOL specs.

Can Pin 1 (B) and Pin 2 (A) be left floating in a design?

No. Floating inputs are prohibited: they cause undefined output states, increased ICC, and potential oscillation due to internal input stage metastability. Per Nexperia's design guidelines, unused inputs must be tied to GND or VCC via ≤10 kΩ resistors. For NOR logic, tying both A and B to GND forces Y = HIGH - a defined, low-power state suitable for default-enable configurations.

How does the IOFF feature behave when VCC is ramping during power-up?

IOFF activates only when VCC falls to 0 V (or ≤0.2 V). During power-up, as VCC rises from 0 V to 2.3 V, the device transitions from high-impedance (IOFF active) to functional operation at ~1.5 V - verified by input threshold tracking. Output Y remains high-impedance until VCC exceeds the minimum functional voltage (~1.8 V), preventing glitch generation on power rails shared with other logic.