Nexperia USA Inc. 74AUP1T04GWH

Overview

74AUP1T04GWH from Nexperia is a single-channel low-power inverting voltage-level translator IC with Schmitt-trigger inputs, operating across 2.3 V to 3.6 V supply, supporting 1.8 V input logic levels while outputting compatible CMOS levels at 2.5 V or 3.3 V. It features IOFF partial power-down protection, <1.5 μA max ICC, and −40 °C to +125 °C operation-used in battery-powered sensor interfaces and mixed-voltage microcontroller I/O bridging.

For engineers reviewing the 74AUP1T04GWH datasheet, 74AUP1T04GWH pinout, 74AUP1T04GWH application, or 74AUP1T04GWH equivalent, key selection criteria include its dual-voltage translation capability, ultra-low static current, IOFF-enabled system power sequencing, and Schmitt-trigger noise immunity across full VCC range.

Technical Context

This device implements a single inverting logic function with hysteresis (VH = 0.15–0.56 V) via integrated Schmitt-trigger inputs, enabling robust operation with slow-rising signals. Its IOFF circuit actively disables outputs during power-down, blocking backflow current when VCC = 0 V.

It supports bidirectional voltage translation: accepts 1.8 V CMOS inputs while powered from 2.5 V or 3.3 V, delivering rail-to-rail output swing (VOH ≥ VCC − 0.11 V, VOL ≤ 0.50 V at 3.0 V), with propagation delay as low as 1.0 ns (CL = 5 pF, VCC = 3.6 V, VI = 3.0–3.6 V).

Key Specifications

Pinout & Package

TSSOP5 (SOT353-1) package: plastic thin shrink small outline, 5-lead, 1.25 mm body width, 0.65 mm lead pitch, exposed pad not present.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar inverting level translation applications.

Compared with SN74LVC1G04DBVR and 74LVC1G14GW, the 74AUP1T04GWH uniquely combines IOFF, Schmitt input, and sub-2 μA ICC in one TSSOP5 device-making it optimal for battery-sensitive, multi-rail, noise-prone embedded systems requiring guaranteed power-state isolation.

Availability

74AUP1T04GWH is available at Aetrix Electronics and suitable for industrial sensor interfaces, wearable battery management systems, automotive body control modules, and IoT edge node GPIO expansion requiring stable component supply across extended temperature and low-power constraints.

Supply support for 74AUP1T04GWH includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a leading Dutch semiconductor manufacturer specializing in high-performance, energy-efficient logic, analog, and MOSFET solutions for automotive, industrial, and consumer markets.

The 74AUP (Advanced Ultra-low Power) product line delivers sub-microamp logic ICs optimized for battery-powered and thermally constrained applications where static power and noise immunity are critical design parameters.

FAQ

Does 74AUP1T04GWH support true bidirectional level translation?

No-it is a unidirectional inverter: input A accepts 1.8 V logic and outputs inverted CMOS levels at VCC (2.5 V or 3.3 V). It does not translate in the reverse direction (Y→A), nor does it support open-drain or bus-switch configurations. Bidirectional translation requires separate devices or dedicated translators like TXB0104.

Can Pin 1 (n.c.) be grounded or left floating in PCB layout?

Pin 1 is internally not connected and must remain unconnected-neither grounded nor tied to any net. Routing copper to it may cause unintended coupling or violate package thermal performance. Standard practice is to omit solder mask opening and avoid trace routing near this pin.

What is the maximum capacitive load the 74AUP1T04GWH output can drive reliably?

The device is characterized up to 30 pF load capacitance with guaranteed propagation delay (tpd ≤ 11.9 ns at −40 °C to +125 °C, VCC = 2.3 V). Driving >30 pF risks increased delay, reduced edge rate, and potential signal integrity issues; for heavier loads, add a buffer stage or reduce trace length and stubs.

How does IOFF behave when VCC is ramping from 0 V to nominal voltage?

IOFF activates when VCC drops below ~0.2 V, disabling the output and limiting leakage to ±0.75 μA. During power-up, IOFF deactivates once VCC exceeds ~0.8 V (typical), after which normal logic operation resumes. This ensures glitch-free startup and prevents bus contention during brown-out conditions.