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Nexperia USA Inc. 74AUP1T1326GT,115
- Part No.:
- 74AUP1T1326GT,115
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 8-XFDFN
- Datasheet:
-
74AUP1T1326GT,115.pdf
- Description:
- IC BUFFER NON-INVERT 3.6V 8XSON
- Quantity:
- Payment:
- Shipping:
Inventory:2,376
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Product details
Overview
74AUP1T1326GT,115 from Nexperia is a single-bit, dual-supply 3-state buffer/line driver with Schmitt-trigger output enable inputs (1OE, 2OE) and logic-level translation capability between independent VCC(A) and VCC(B) rails (1.1 V–3.6 V). It integrates OR-gated enable control, delivers 1Y output directly from the OR gate, and supports partial power-down via IOFF circuitry. It is used in low-voltage I/O bridging between mixed-voltage subsystems such as 1.8 V MCU GPIO and 3.3 V peripheral interfaces.
For engineers reviewing the 74AUP1T1326GT,115 datasheet, 74AUP1T1326GT,115 pinout, 74AUP1T1326GT,115 application, or 74AUP1T1326GT,115 equivalent, key selection criteria include dual-rail voltage flexibility, Schmitt-trigger noise immunity on enable inputs, guaranteed high-impedance state under dual-OE control, IOFF-enabled safe power sequencing, and XSON8 package suitability for space-constrained PCB layouts.
Technical Context
The device implements an OR-gated dual-output-enable architecture where 1OE and 2OE-each referenced to VCC(A)-drive a shared logic gate whose output appears at pin 1Y; only when both are LOW does output 2Y enter high-impedance. Input A and output 2Y are referenced to VCC(B), enabling true bidirectional voltage translation across isolated supply domains.
Its Schmitt-trigger inputs provide hysteresis (VH = 0.08 V to 1.31 V depending on VCC(A)), ensuring clean edge generation from slow or noisy signals. The IOFF circuit actively disables outputs during power-down, blocking backflow current when either VCC(A) or VCC(B) is at 0 V, satisfying JEDEC JESD78 Class II latch-up and partial-power-down requirements.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC(A) Range | 1.1 V to 3.6 V: Enables interface with 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V logic domains on enable/control side. |
| VCC(B) Range | 1.1 V to 3.6 V: Supports data path translation between any two compatible low-voltage rails, e.g., 1.8 V → 3.3 V. |
| IOFF Leakage | ±0.2 μA max: Prevents damaging back-current when one supply is powered off while the other remains active. |
| Propagation Delay | 1.2 ns to 9.5 ns (CL = 5 pF): Delivers sub-nanosecond timing margin at 3.3 V, scaling predictably with VCC and load capacitance. |
| Hysteresis Voltage VH | 0.08 V to 1.31 V (VCC(A)-dependent): Rejects noise up to ±650 mV on OE inputs without false triggering. |
| Static ICC(A) | 0.9 μA max: Ensures ultra-low quiescent power in always-on system management or battery-backed circuits. |
Pinout & Package
XSON8 (SOT833-1) package: 1 × 1.95 × 0.5 mm body, no leads, wettable flanks, thermal pad not present.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC(B) | Supply voltage B | Power rail for data input A and output 2Y; defines VOH/VOL thresholds for 2Y. |
| A | Data input | Single-bit data input referenced to VCC(B); accepts up to 3.6 V regardless of VCC(B). |
| VCC(A) | Supply voltage A | Power rail for OE inputs and output 1Y; sets VT+, VT−, and hysteresis for enable logic. |
| GND | Ground (0 V) | Common reference for all voltage measurements and current return paths. |
| 1OE | Output enable input A | Schmitt-trigger input referenced to VCC(A); controls OR-gate stage and 1Y output. |
| 2OE | Output enable input B | Schmitt-trigger input referenced to VCC(A); second input to OR gate driving 1Y and gating 2Y. |
| 1Y | OR-gate output | Direct logic-level output of (1OE OR 2OE); provides status indication of enable condition. |
| 2Y | Data output | 3-state buffered output of A, enabled only when both 1OE and 2OE are LOW; referenced to VCC(B). |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent supply rails | VCC(A) and VCC(B) operate independently from 1.1 V to 3.6 V, enabling robust level-shifting without external components. |
| IOFF partial power-down protection | Blocks >99.9% of backflow current when either supply is at 0 V, eliminating need for external isolation diodes. |
| Schmitt-trigger OE inputs with hysteresis | VT+ and VT− thresholds differ by VH (0.08–1.31 V), rejecting noise on enable lines in electrically noisy environments. |
| Ultra-low static power | ICC(A) ≤ 0.9 μA ensures negligible battery drain in always-on monitoring or wake-up circuits. |
| JEDEC-compliant interface levels | Meets JESD8-7 (1.2–1.95 V), JESD8-5 (1.8–2.7 V), and JESD8-B (2.7–3.6 V) standards for interoperability across voltage nodes. |
Applications
| USB-C Power Delivery Controller Interface | Industrial Sensor Hub Signal Conditioning |
|---|---|
Use Scenario: Isolating and translating GPIO control signals between a 1.8 V PD controller and a 3.3 V USB-C port manager IC. IC Role / Device Role / Timing Role: Dual-rail buffer providing direction-controlled level translation with precise 3-state control synchronized to PD protocol timing windows. Use Value: Eliminates discrete level-shifters and reduces BOM count while guaranteeing glitch-free enable transitions via Schmitt-triggered OE inputs. | Use Scenario: Interfacing multiple 1.2 V analog sensor outputs to a 2.5 V ADC interface bus in a programmable logic controller. IC Role / Device Role / Timing Role: Low-noise, low-power line driver buffering sensor data lines with hysteresis-filtered enable control for synchronized sampling windows. Use Value: Reduces signal integrity risk from slow-rising sensor enable signals and maintains <10 % VCC overshoot/undershoot per JEDEC spec. |
| Automotive Body Control Module I/O Expansion | Low-Power Wearable Device Subsystem Bridge |
Use Scenario: Extending microcontroller I/O to drive 3.3 V CAN transceiver control pins from a 1.5 V core domain in a BCM. IC Role / Device Role / Timing Role: Safe, IOFF-protected buffer enabling hot-swap-compatible power sequencing between core logic and peripheral supplies. Use Value: Prevents latch-up and backfeed during supply ramp-up/down sequences, meeting AEC-Q100 stress test requirements for automotive grade operation. | Use Scenario: Bridging a 1.8 V Bluetooth SoC's GPIO to a 2.8 V display driver IC in a hearable device with strict leakage budget. IC Role / Device Role / Timing Role: Ultra-low-leakage (±0.1 μA) 3-state buffer enabling dynamic power gating of display subsystem during sleep mode. Use Value: Achieves sub-μA system standby current by combining IOFF shutdown with 0.9 μA ICC(A) quiescent draw. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-supply buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1T34DBVR | Single-supply only (1.65–5.5 V); no Schmitt-trigger OE; no IOFF; no dual-rail translation. | Limited to same-voltage-domain buffering; unsuitable for mixed-rail translation or partial power-down. | Select only when interfacing within one voltage node and IOFF/Schmitt features are unnecessary. |
| 74AVC1T34GW,125 | Single-supply (1.2–3.6 V); includes Schmitt-trigger input but no dual-OE OR logic or 1Y status output. | Supports noise-immune input but lacks dual-enable coordination and explicit enable-status feedback required for safety-critical sequencing. | Choose when only input hysteresis is needed and coordinated dual-OE control is not part of the system architecture. |
Compared with SN74LVC1T34DBVR and 74AVC1T34GW,125, the 74AUP1T1326GT,115 uniquely delivers dual-rail translation, OR-gated dual-OE control with status output 1Y, and IOFF protection-making it the only option among the three that satisfies simultaneous mixed-voltage bridging, deterministic 3-state entry, and safe power-down in systems with asynchronous supply sequencing.
Availability
74AUP1T1326GT,115 is available at Aetrix Electronics and suitable for USB-C PD implementations, industrial sensor hubs, automotive body control modules, and low-power wearable subsystem bridges requiring stable component supply across extended temperature (-40 °C to +85 °C) and long-lifecycle production.
Supply support for 74AUP1T1326GT,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance, reliable, and energy-efficient logic, discrete, and MOSFET solutions with focus on automotive, industrial, and mobile markets.
The 74AUP family targets ultra-low-power, dual-supply logic applications requiring robust noise immunity, precise voltage translation, and safe power sequencing-designed specifically for next-generation portable, automotive, and IoT edge devices.
FAQ
What is the function of pin 1Y?
Pin 1Y outputs the logical OR of the two Schmitt-trigger enable inputs (1OE and 2OE), providing real-time status of the enable condition. When either 1OE or 2OE is HIGH, 1Y goes HIGH; only when both are LOW does 1Y go LOW. This enables external monitoring of the 2Y output enable state without probing the data path.
Can VCC(A) and VCC(B) be powered from different sources with independent ramp-up timing?
Yes. The IOFF circuitry ensures that when either VCC(A) or VCC(B) is at 0 V, the corresponding outputs (1Y or 2Y) are safely disabled with leakage ≤ ±0.2 μA. This allows fully asynchronous power sequencing-e.g., VCC(B) can be active while VCC(A) ramps, or vice versa-without risk of back-current or latch-up.
How does the Schmitt-trigger hysteresis improve system reliability?
The hysteresis (VH = VT+ − VT−) ranges from 0.08 V to 1.31 V depending on VCC(A), rejecting noise spikes and slow-edge interference on OE inputs. For example, at VCC(A) = 3.0 V, VT+ = 2.29 V and VT− = 1.24 V, giving 1.05 V noise margin-preventing false toggling during ESD events or board-level crosstalk in dense PCB layouts.
Is the XSON8 package compatible with standard reflow profiles and automated optical inspection?
Yes. The SOT833-1 (XSON8) package uses a leadless, wettable flank design optimized for IPC-A-610 Class 2/3 assembly. Its 0.5 mm pitch, 1.95 mm length, and exposed copper terminals support full-profile reflow (J-STD-020 compliant) and high-accuracy AOI detection of solder joint integrity without shadowing issues.
74AUP1T1326GT,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AUP
- Package/Case:
- 8-XFDFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 6mA, 6mA
- Voltage - Supply:
- 1.1V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-XSON, SOT833-1 (1.95x1)
74AUP1T1326GT,115 FAQ
1.How can I place an order for 74AUP1T1326GT,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP1T1326GT,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP1T1326GT,115 reliable?
The price and inventory of 74AUP1T1326GT,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1T1326GT,115 is usually 5 days.
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4.How is shipping managed for 74AUP1T1326GT,115?
74AUP1T1326GT,115 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP1T1326GT,115 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP1T1326GT,115?
For technical support, including 74AUP1T1326GT,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1T1326GT,115 requirements.
6.How does Aetrix verify that 74AUP1T1326GT,115 is sourced from the original manufacturer or authorized distributors?
All 74AUP1T1326GT,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1T1326GT,115 meets industry standards.
7.What is the process for return or replacement of 74AUP1T1326GT,115?
All 74AUP1T1326GT,115 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1T1326GT,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP1T1326GT,115 part is unused and in its original packaging.
Return procedure for 74AUP1T1326GT,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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