Nexperia USA Inc. 74AUP1T34GM,115
- Part No.:
- 74AUP1T34GM,115
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 6-XFDFN
- Datasheet:
-
74AUP1T34GM,115.pdf
- Description:
- IC TRANSLTR UNIDIRECTIONAL 6XSON
- Quantity:
- Payment:

- Shipping:

Inventory:116,530
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Product details
Overview
74AUP1T34GM,115 from Nexperia is a single-channel dual-supply translating buffer with independent VCC(A) and VCC(Y) rails (1.1 V to 3.6 V), Schmitt-trigger inputs for noise immunity, IOFF partial power-down protection, and guaranteed operation from −40 °C to +125 °C in the XSON6 (SOT886) package. It enables level translation between mismatched logic domains in ultra-low-power portable and battery-powered systems.
For engineers reviewing the 74AUP1T34GM,115 datasheet, 74AUP1T34GM,115 pinout, 74AUP1T34GM,115 application, or 74AUP1T34GM,115 equivalent, key selection criteria include dual-rail voltage flexibility, sub-1 µA static ICC, IOFF leakage < ±0.2 µA at power-down, and propagation delay as low as 1.4 ns (VCC = 3.3 V, CL = 5 pF).
Technical Context
This device implements a unidirectional A→Y buffer with input referenced to VCC(A) and output referenced to VCC(Y), enabling true bidirectional voltage domain isolation. The Schmitt-trigger input threshold (e.g., VIH = 0.65×VCC(A) min at 1.1 V) ensures robustness against slow-rising signals and EMI in noisy environments.
IOFF circuitry actively disables the output when either supply is near 0 V, preventing backflow current and enabling hot-insertion in multi-rail systems. The design complies with JEDEC standards JESD8-7, JESD8-5, and JESD8-B across its full operating range.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Range | VCC(A): 1.1 V to 3.6 V; VCC(Y): 1.1 V to 3.6 V - supports mixed-voltage interconnects (e.g., 1.2 V MCU to 3.3 V peripheral) |
| Static Current | ICC ≤ 0.9 µA max - enables always-on signal conditioning in energy-constrained IoT nodes |
| IOFF Leakage | ±0.2 µA max - prevents damaging back-current during partial system shutdown |
| Propagation Delay | 1.4 ns min (CL = 5 pF, VCC = 3.0 V) - meets timing requirements for high-speed interface bridging |
| Input Threshold | VIH = 0.65×VCC(A) min (1.1 V range); VIL = 0.35×VCC(A) max - Schmitt hysteresis improves noise margin by ≥150 mV |
| Operating Temp | −40 °C to +125 °C - qualified for automotive under-hood and industrial control applications |
| ESD Rating | HBM > 5000 V, CDM > 1000 V - withstands handling and board-level ESD events without protection diodes |
Pinout & Package
XSON6 plastic extremely thin small outline package (SOT886); no leads; 6 terminals; body dimensions 1.0 × 1.45 × 0.5 mm; thermal pad optional; pin 1 indicator located on lower-left corner below marking code "pQ".
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A | Data Input | Signal referenced to VCC(A); accepts 0–3.6 V with Schmitt-trigger action |
| VCC(A) | Input-Side Supply | Powers input stage and defines VIH/VIL thresholds; decoupling required |
| GND | Ground Reference | Common return path for both supply domains; must be low-impedance |
| n.c. | No Connect | Internally unconnected terminal; left floating per datasheet |
| VCC(Y) | Output-Side Supply | Powers output stage and sets VOH/VOL levels; independent of VCC(A) |
| Y | Data Output | Buffered, translated output referenced to VCC(Y); drives capacitive loads ≤30 pF |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent supply rails | Enables seamless 1.2 V ↔ 3.3 V, 1.8 V ↔ 2.5 V, or other asymmetric logic translations without external resistors |
| IOFF partial power-down | Prevents back-current flow when either VCC(A) or VCC(Y) is powered off - critical for hot-swap and power-gating architectures |
| Schmitt-trigger input | Provides ≥150 mV hysteresis at 1.2 V supply, eliminating need for external RC filtering on slow GPIO lines |
| Ultra-low dynamic power | CPD = 4.6 pF at 3.3 V enables <1 µW dynamic dissipation at 1 MHz - extends battery life in wearables |
| Wide temperature qualification | Specified over −40 °C to +125 °C - suitable for engine control units and industrial motor drives |
Applications
| Industrial Sensor Interface | Automotive Body Control Module |
|---|---|
Use Scenario: Interfacing a 1.2 V MEMS pressure sensor to a 3.3 V CAN transceiver microcontroller input. IC Role / Device Role: Level-translating buffer isolating supply domains while preserving signal integrity. Use Value: Eliminates need for discrete FET translators; IOFF prevents sensor-side current leakage during MCU sleep mode. | Use Scenario: Driving a 2.5 V LIN bus transceiver enable pin from a 1.8 V ASIL-B microcontroller GPIO. IC Role / Device Role: Voltage-domain bridging buffer with fail-safe power-down behavior. Use Value: Schmitt input rejects ignition noise; IOFF guarantees zero current draw if LIN supply fails while MCU remains active. |
| Portable Medical Device | Smart Energy Meter |
Use Scenario: Connecting a 1.1 V ultra-low-power ADC output to a 3.0 V display controller in a battery-operated glucose monitor. IC Role / Device Role: Low-quiescent-current signal translator maintaining timing accuracy. Use Value: ICC ≤ 0.9 µA adds negligible load to coin-cell battery; 1.4 ns tPD preserves sampling window integrity. | Use Scenario: Isolating a 1.8 V metrology SoC from a 3.3 V PLC communication interface in a DIN-rail meter. IC Role / Device Role: Dual-rail buffer enabling independent power sequencing and fault containment. Use Value: Independent VCC(A)/VCC(Y) allows metering core to remain active during comms module reset or brownout. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-supply translating buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1T34DBVR | Single-supply only (1.65–5.5 V); no independent VCC(A)/VCC(Y); higher ICC (10 µA typ) | Cannot translate between mismatched rails; lacks IOFF and Schmitt input | Select only when both sides share same supply and noise immunity is non-critical |
| TXB0101DCKR | Auto-direction sensing; higher propagation delay (5.2 ns min); larger X2SON6 package (1.45 × 1.0 mm) | Requires no direction control signal but consumes more board area and power | Prefer for bidirectional data paths; avoid when strict unidirectional timing or space constraints apply |
Compared with SN74LVC1T34DBVR and TXB0101DCKR, the 74AUP1T34GM,115 uniquely delivers rail-to-rail translation with sub-µA static current, Schmitt noise rejection, and minimal footprint - making it optimal for space- and power-constrained unidirectional interfaces.
Availability
74AUP1T34GM,115 is available at Aetrix Electronics and suitable for industrial sensor interfaces, automotive body electronics, portable medical devices, and smart energy meters requiring stable component supply across extended temperature ranges.
Supply support for 74AUP1T34GM,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance, reliable, and scalable components for automotive, industrial, and consumer markets.
The 74AUP1T34 belongs to Nexperia's Advanced Ultra-low Power (AUP) logic family, engineered specifically for battery-powered and thermally constrained applications demanding nanowatt static power and robust signal integrity across wide voltage and temperature ranges.
FAQ
Can 74AUP1T34GM,115 translate from 3.3 V to 1.2 V while maintaining valid logic levels?
Yes. With VCC(A) = 3.3 V and VCC(Y) = 1.2 V, the device outputs valid 1.2 V logic levels (VOH ≥ 1.11 V, VOL ≤ 0.31 V at 1.9 mA) while accepting standard 3.3 V CMOS inputs. VIH minimum is 2.0 V at 3.3 V supply, ensuring reliable detection of high states.
What is the maximum capacitive load the Y output can drive reliably?
The Y output is characterized up to 30 pF load capacitance across all voltage/temperature conditions. At VCC(Y) = 3.0 V and CL = 30 pF, tPD remains ≤ 3.4 ns (−40 °C to +125 °C), confirming stable operation into typical PCB traces and IC inputs without added series resistance.
Does the n.c. pin on SOT886 require PCB routing or grounding?
No. Pin 5 (n.c.) is internally unconnected and must be left floating on the PCB. Routing or grounding this terminal may cause mechanical stress or unintended coupling; Nexperia specifies it as "not connected" in Table 3 and Figure 6.
How does IOFF behave when only VCC(Y) is powered and VCC(A) = 0 V?
When VCC(A) = 0 V and VCC(Y) = 3.3 V, the IOFF circuit disables the output stage, limiting Y-terminal leakage to ±0.2 µA max. This prevents current from flowing backward into the unpowered A-side circuit - a critical feature for power-domain isolation in modular systems.
74AUP1T34GM,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AUP
- Package/Case:
- 6-XFDFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- Push-Pull
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 1.1V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-XSON, SOT886 (1.45x1)
74AUP1T34GM,115 FAQ
1.How can I place an order for 74AUP1T34GM,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP1T34GM,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
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The price and inventory of 74AUP1T34GM,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1T34GM,115 is usually 5 days.
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6.How does Aetrix verify that 74AUP1T34GM,115 is sourced from the original manufacturer or authorized distributors?
All 74AUP1T34GM,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1T34GM,115 meets industry standards.
7.What is the process for return or replacement of 74AUP1T34GM,115?
All 74AUP1T34GM,115 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1T34GM,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP1T34GM,115 part is unused and in its original packaging.
Return procedure for 74AUP1T34GM,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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