Nexperia USA Inc. 74AUP1T34GN,132
- Part No.:
- 74AUP1T34GN,132
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 6-XFDFN
- Datasheet:
-
74AUP1T34GN,132.pdf
- Description:
- IC TRANSLTR UNIDIRECTIONAL 6XSON
- Quantity:
- Payment:

- Shipping:

Inventory:4,595
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Product details
Overview
74AUP1T34GN,132 from Nexperia is a single-channel dual-supply voltage-translating buffer with independent VCC(A) and VCC(Y) rails (1.1 V to 3.6 V each), Schmitt-trigger inputs for noise immunity, IOFF partial power-down protection, and operation across –40 °C to +125 °C. It enables level-shifting between disparate logic domains in ultra-low-power IoT sensor nodes, battery-powered wearables, and mixed-voltage microcontroller interfaces.
For engineers reviewing the 74AUP1T34GN,132 datasheet, 74AUP1T34GN,132 pinout, 74AUP1T34GN,132 application, or 74AUP1T34GN,132 equivalent, this device is selected for its sub-1 µA static ICC, dual-rail flexibility, guaranteed propagation delay ≤9.3 ns (VCC=3.0 V, CL=5 pF), and XSON6 package compatibility with high-density PCB layouts.
Technical Context
The 74AUP1T34GN implements a unidirectional A→Y buffer with input referenced to VCC(A) and output referenced to VCC(Y), enabling asynchronous voltage translation without clock or direction control. Its Schmitt-trigger input threshold (VIH/VIL varying with VCC(A)) ensures robust operation with slow-rising signals and high noise margins.
IOFF circuitry actively disables the output when either supply is at 0 V, blocking backflow current and supporting hot-swap and partial power-down system architectures. The device complies with JEDEC standards JESD8-7, JESD8-5, and JESD8-B across its full operating range.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC(A) Range | 1.1 V to 3.6 V - supports input logic from 1.2 V I²C up to 3.3 V GPIO |
| VCC(Y) Range | 1.1 V to 3.6 V - independently powers output to match target domain (e.g., 1.8 V FPGA bank) |
| ICC (max) | 0.9 µA - enables multi-year battery life in always-on sensor hubs |
| tpd (max) | 9.3 ns @ VCC=3.0 V, CL=5 pF - meets timing budgets for 50 MHz data paths |
| IOFF Leakage | ±0.75 µA - prevents bus contention during MCU sleep mode transitions |
| Operating Temp | –40 °C to +125 °C - qualified for under-hood automotive and industrial edge controllers |
| ESD HBM | >5000 V - withstands handling and board-level ESD events without protection diodes |
Pinout & Package
XSON6 package (SOT1115): 0.9 mm × 1.0 mm × 0.35 mm body, 6-terminal no-lead surface-mount, thermal-enhanced construction for high-density routing and low thermal resistance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | VCC(A) | Input-side supply rail - powers Schmitt-trigger input stage and defines VIH/VIL thresholds |
| 2 | A | Data input - accepts logic levels referenced to VCC(A); immune to slow edges due to hysteresis |
| 3 | GND | Common reference - mandatory 0 V connection for both supply domains' return paths |
| 4 | Y | Data output - drives logic levels referenced to VCC(Y); supports 4 mA sink/source |
| 5 | n.c. | No connect - internal die pad left floating; no external connection required |
| 6 | VCC(Y) | Output-side supply rail - sets VOH/VOL levels and powers output driver stage |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent supply rails | VCC(A) and VCC(Y) operate simultaneously at different voltages (e.g., 1.8 V → 3.3 V), eliminating need for external level-shifters |
| Schmitt-trigger input | Hysteresis ≥0.3×VCC(A) ensures reliable switching with noisy or slow-rising signals in motor-control feedback loops |
| IOFF partial power-down | Output automatically high-impedance when VCC(Y) = 0 V, preventing backfeed into powered subsystems during firmware updates |
| Ultra-low ICC | Typical 0.5 µA at 1.2 V enables integration into energy-harvesting systems with µW power budgets |
| Wide temperature range | Specified from –40 °C to +125 °C supports deployment in automotive ADAS camera modules and industrial PLC I/O cards |
Applications
| Automotive Camera Interface | Industrial Sensor Hub |
|---|---|
Use Scenario: Translating MIPI I²C control signals (1.8 V) from SoC to image sensor requiring 2.8 V I/O. IC Role / Device Role / Timing Role: Unidirectional voltage translator buffering configuration commands with <9.3 ns delay and zero hold-time violation. Use Value: Eliminates discrete MOSFET-based level shifters, reducing BOM count and layout area by 60%. | Use Scenario: Interfacing 3.3 V microcontroller UART to multiple 1.2 V environmental sensors (temperature, humidity, gas). IC Role / Device Role / Timing Role: Single-channel bidirectional-capable buffer (A→Y only) enabling shared bus arbitration without signal inversion. Use Value: Maintains signal integrity across mixed-voltage domains while consuming <1 µA in idle state. |
| Wearable Health Monitor | Smart Energy Meter |
Use Scenario: Level-shifting accelerometer interrupt signals (1.1 V logic) to 2.5 V BLE SoC wake-up input. IC Role / Device Role / Timing Role: Schmitt-trigger input rejects EMI from adjacent RF sections; IOFF prevents leakage during deep-sleep modes. Use Value: Extends coin-cell battery life beyond 2 years by minimizing quiescent current in always-on sensing path. | Use Scenario: Isolating 3.3 V metering ASIC SPI interface from 1.8 V secure element during cryptographic key exchange. IC Role / Device Role / Timing Role: Dual-rail buffer enforces clean voltage domain separation while meeting <10 ns setup/hold timing for secure boot sequences. Use Value: Meets IEC 62056-21 isolation requirements without optocouplers or complex power sequencing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar voltage-translating buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1T34DBVR | Single-supply (VCC only); no independent VCC(A)/VCC(Y); max VCC = 5.5 V; higher ICC (10 µA typical) | Requires matched input/output voltage; unsuitable for true dual-rail translation (e.g., 1.2 V → 3.3 V) | Select only when both sides share same rail and higher speed (tPD = 3.5 ns) is prioritized over ultra-low power |
| TXB0101DCKR | Auto-direction-sensing; supports bidirectional translation; higher ICC (10 µA typical); requires external enable | Designed for I²C/SPI bidirectional buses; adds complexity for simple unidirectional use cases | Choose only when bus direction changes dynamically; avoid for fixed A→Y paths due to unnecessary overhead |
Compared with SN74LVC1T34DBVR and TXB0101DCKR, the 74AUP1T34GN,132 uniquely delivers true independent dual-supply operation with sub-1 µA ICC and guaranteed –40 °C to +125 °C performance, making it optimal for space-constrained, battery-sensitive, and thermally demanding applications where rail isolation is mandatory.
Availability
74AUP1T34GN,132 is available at Aetrix Electronics and suitable for automotive camera interfaces, industrial sensor hubs, wearable health monitors, and smart energy meters requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74AUP1T34GN,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance, high-reliability logic, analog, and MOSFET solutions with leadership in efficiency, miniaturization, and thermal performance.
The 74AUP1T34GN,132 belongs to Nexperia's Advanced Ultra-low Power (AUP) logic family, engineered specifically for battery-powered and thermally constrained applications demanding minimal static/dynamic power without sacrificing timing performance or ruggedness.
FAQ
What is the maximum allowable voltage difference between VCC(A) and VCC(Y)?
The datasheet does not specify a maximum differential voltage limit. Both supplies are rated from 1.1 V to 3.6 V independently, and operation is fully characterized for any combination within that range (e.g., VCC(A) = 1.1 V, VCC(Y) = 3.6 V). Absolute maximum ratings allow each supply up to +4.6 V, but functional operation is only guaranteed within the 1.1 V–3.6 V window.
Does the 74AUP1T34GN,132 support bidirectional signal translation?
No. The 74AUP1T34GN,132 is a unidirectional buffer with fixed A→Y signal flow. It lacks auto-direction sensing or enable-controlled bi-directionality. For bidirectional translation, devices like the TXB0101 or PCA9306 are required - but those incur higher power and complexity versus this part's optimized single-path design.
Can the n.c. pin (Pin 5) be left floating or must it be grounded?
Pin 5 is explicitly designated "n.c." (no connect) in the datasheet and pin description table. It is an internal die pad with no electrical connection to active circuitry. It may be left unconnected on the PCB; grounding or tying to VCC provides no functional benefit and is not recommended unless required by mechanical or thermal design constraints.
How does the Schmitt-trigger input improve system reliability in noisy environments?
The Schmitt-trigger input provides hysteresis (typically ≥0.3×VCC(A)), meaning VIH and VIL thresholds differ by ~300 mV at 1.2 V supply. This prevents multiple output toggles caused by slow or noisy input edges crossing a single threshold, ensuring clean, glitch-free output transitions in motor-drive feedback, industrial sensor lines, or RF-adjacent circuits.
74AUP1T34GN,132 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AUP
- Package/Case:
- 6-XFDFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- Push-Pull
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 1.1V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-XSON (0.9x1)
74AUP1T34GN,132 FAQ
1.How can I place an order for 74AUP1T34GN,132 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP1T34GN,132 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP1T34GN,132 reliable?
The price and inventory of 74AUP1T34GN,132 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1T34GN,132 is usually 5 days.
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5.How can I obtain technical support or documentation for 74AUP1T34GN,132?
For technical support, including 74AUP1T34GN,132 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1T34GN,132 requirements.
6.How does Aetrix verify that 74AUP1T34GN,132 is sourced from the original manufacturer or authorized distributors?
All 74AUP1T34GN,132 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1T34GN,132 meets industry standards.
7.What is the process for return or replacement of 74AUP1T34GN,132?
All 74AUP1T34GN,132 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1T34GN,132, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP1T34GN,132 part is unused and in its original packaging.
Return procedure for 74AUP1T34GN,132:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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