Nexperia USA Inc. 74AUP1T34GW,125
- Part No.:
- 74AUP1T34GW,125
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 5-TSSOP, SC-70-5, SOT-353
- Datasheet:
-
74AUP1T34GW,125.pdf
- Description:
- IC TRANSLATOR UNIDIR 5TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:29,628
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Product details
Overview
74AUP1T34GW,125 from Nexperia is a single-channel dual-supply voltage-translating buffer with independent VCC(A) and VCC(Y) rails (1.1 V to 3.6 V each), Schmitt-trigger inputs for noise immunity, and IOFF partial power-down protection. It delivers ultra-low static current (≤0.9 µA max), supports −40 °C to +125 °C operation, and enables level-shifting between disparate logic domains in battery-powered IoT sensors and low-voltage microcontroller interfaces.
For engineers reviewing the 74AUP1T34GW,125 datasheet, 74AUP1T34GW,125 pinout, 74AUP1T34GW,125 application, or 74AUP1T34GW,125 equivalent, this device is selected for precise bidirectional voltage translation where rail isolation, sub-1-µA quiescent current, and guaranteed operation down to 1.1 V on both ports are required - not for general-purpose buffering or high-speed clock distribution.
Technical Context
The 74AUP1T34GW,125 implements a non-inverting buffer with input referenced to VCC(A) and output referenced to VCC(Y), enabling true dual-rail translation without internal level-shift circuitry. Its Schmitt-trigger input threshold (e.g., VIH = 0.65×VCC(A) min at 1.1 V) ensures robust operation with slow-rising signals common in sensor interfaces and wake-up circuits.
IOFF functionality actively disables the output when either supply is near 0 V, blocking backflow current and preventing bus contention during partial system power-down - a critical requirement in multi-rail portable systems with asymmetric power sequencing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Range (VCC(A)/VCC(Y)) | 1.1 V to 3.6 V each - enables translation between 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains |
| Max ICC (Static) | 0.9 µA - ensures <1 µW static power at 1.2 V, critical for always-on sensor nodes |
| Propagation Delay (CL = 5 pF) | 1.4 ns to 25.9 ns - varies with VCC combination; e.g., 1.9 ns at 3.0 V → 3.0 V, 25.9 ns at 1.1 V → 1.1 V |
| IOFF Leakage (Y output) | ±0.75 µA max - prevents >0.5 µA backfeed current when VCC(Y) = 0 V and VI = 3.6 V |
| Input Threshold (VIH/VIL) | VIL ≤ 0.3×VCC(A), VIH ≥ 0.7×VCC(A) - Schmitt hysteresis improves noise margin by ≥150 mV at 1.8 V |
| Operating Temperature | −40 °C to +125 °C - qualified for under-hood automotive and industrial edge controllers |
| ESD Rating (HBM) | 5000 V - exceeds JEDEC JS-001 Class 3A, suitable for handling in uncontrolled environments |
Pinout & Package
TSSOP5 package (SOT353-1): 5-lead plastic thin shrink small outline, 1.25 mm body width, 0.65 mm pitch, exposed pad not present.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | VCC(A) | Input-side supply rail - powers input stage and defines VIH/VIL thresholds |
| 2 | A | Non-inverting data input with Schmitt-trigger action - accepts slow edges down to 200 ns/V |
| 3 | GND | Common reference ground for both supply domains - must be low-impedance |
| 4 | Y | Output referenced to VCC(Y) - drives loads up to ±20 mA with VOH ≥ VCC(Y) − 0.1 V |
| 5 | VCC(Y) | Output-side supply rail - sets output swing and drive strength independently of VCC(A) |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent supply rails | VCC(A) and VCC(Y) operate from 1.1 V to 3.6 V simultaneously - no shared rail constraint |
| IOFF partial power-down | Output Y is high-impedance when VCC(Y) = 0 V, preventing back-current even if A is driven high |
| Schmitt-trigger input | Hysteresis ≥150 mV at 1.8 V - rejects noise spikes and stabilizes signal integrity on long PCB traces |
| Ultra-low dynamic power | CPD = 3.8–4.6 pF - limits switching power to <1 µW at 1 MHz/1.2 V, ideal for duty-cycled sensors |
| Wide temperature range | Specified from −40 °C to +125 °C - validated for automotive cabin and industrial control environments |
Applications
| Industrial Sensor Interface | Low-Power Microcontroller I/O Expansion |
|---|---|
|
Use Scenario: Connecting a 1.2 V MEMS accelerometer to a 3.3 V MCU GPIO while maintaining signal integrity during deep-sleep mode. IC Role / Device Role / Timing Role: Voltage translator isolating supply domains and enabling IOFF shutdown when MCU is powered off. Use Value: Eliminates need for external pull-ups or discrete FETs; reduces BOM count by one active component and cuts leakage by >90% vs. resistor-based translation. |
Use Scenario: Extending I²C bus from a 1.8 V SoC to 2.5 V EEPROM and 3.3 V ADC in a wearable health monitor. IC Role / Device Role / Timing Role: Bidirectional level shifter with rail-independent timing - preserves I²C rise/fall time compliance across voltages. Use Value: Enables mixed-voltage I²C without bus contention; Schmitt input tolerates slow edges from capacitive touch sensors sharing same bus. |
| Automotive Body Control Module | Battery-Powered Edge Node |
|
Use Scenario: Interfacing a 5 V legacy LIN transceiver input with a 1.2 V ASIL-B microcontroller's wake-up pin. IC Role / Device Role / Timing Role: Input-level translator with hysteresis - converts 5 V LIN pulses to clean 1.2 V logic-compatible signals. Use Value: Replaces discrete resistor-divider + comparator solution; reduces footprint by 60% and eliminates calibration drift over temperature. |
Use Scenario: Enabling ultra-low-power BLE SoC (1.1 V core) to communicate with 1.8 V environmental sensor via SPI. IC Role / Device Role / Timing Role: Low-leakage SPI signal translator - maintains IOFF state during SoC sleep to prevent sensor power drain. Use Value: Achieves <100 nA system standby current; propagation delay <2 ns at 1.1 V → 1.8 V ensures timing closure at 2 MHz SPI. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-supply translating buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1T34DBVR | Single-supply only (1.65 V–5.5 V); no independent VCC(A)/VCC(Y); IOFF supported | Cannot translate between mismatched rails (e.g., 1.2 V → 3.3 V); requires shared VCC | Select only when both sides use same voltage and space constraints favor TI's SOT-23-5 |
| TXB0101DCKR | Auto-direction sensing; 1.2 V–3.6 V dual-rail; higher ICC (10 µA typ); no Schmitt input | Unidirectional use requires external direction control; susceptible to noise on slow edges | Prefer when bidirectional data flow needed, but avoid in noisy sensor wake-up paths |
Compared with SN74LVC1T34DBVR and TXB0101DCKR, the 74AUP1T34GW,125 uniquely combines independent dual-rail support, sub-1-µA static current, and Schmitt-trigger noise immunity - making it the only choice for ultra-low-power, mixed-voltage, noise-prone sensor interface applications.
Availability
74AUP1T34GW,125 is available at Aetrix Electronics and suitable for industrial sensor interfaces, automotive body electronics, and battery-powered edge nodes requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74AUP1T34GW,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance, reliable standard products for automotive, industrial, and mobile markets.
The 74AUP (Advanced Ultra-low Power) logic family targets ultra-low-power mixed-voltage digital interfacing - specifically engineered for energy-constrained applications where rail independence, nanowatt static consumption, and robust noise immunity are mandatory.
FAQ
Can 74AUP1T34GW,125 translate from 3.3 V input to 1.2 V output?
Yes. With VCC(A) = 3.3 V and VCC(Y) = 1.2 V, the device operates within its specified 1.1 V–3.6 V dual-rail range. VIH is guaranteed ≥2.0 V at 3.3 V, ensuring compatibility with standard 3.3 V CMOS outputs; VOH remains ≥1.1 V (VCC(Y) − 0.1 V), meeting 1.2 V logic-high requirements.
Does the IOFF feature work when only VCC(A) is powered?
Yes. When VCC(Y) = 0 V and VCC(A) = 1.1–3.6 V, the IOFF circuit forces output Y into high-impedance state regardless of input A voltage. Measured Y-output leakage is ≤±0.75 µA, preventing back-current into a powered-down 1.2 V domain.
What is the minimum load capacitance this device can drive reliably?
The device is characterized down to CL = 5 pF, with propagation delay and output drive fully specified at that load. Driving lower capacitances (e.g., 2 pF PCB trace) is functional but may increase ringing; output rise/fall times scale linearly with CL, so sub-5 pF loads remain within 10% overshoot limits per datasheet.
Is the Schmitt-trigger input compatible with analog sensor outputs?
No. The Schmitt-trigger is designed for digital logic-level signals, not analog waveforms. Its hysteresis (typically ~200 mV at 1.8 V) distorts analog voltage transitions and introduces quantization error; use dedicated comparators or ADCs for true analog signal conditioning.
74AUP1T34GW,125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AUP
- Package/Case:
- 5-TSSOP, SC-70-5, SOT-353
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- Push-Pull
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 1.1V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 5-TSSOP
74AUP1T34GW,125 FAQ
1.How can I place an order for 74AUP1T34GW,125 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP1T34GW,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
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6.How does Aetrix verify that 74AUP1T34GW,125 is sourced from the original manufacturer or authorized distributors?
All 74AUP1T34GW,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1T34GW,125 meets industry standards.
7.What is the process for return or replacement of 74AUP1T34GW,125?
All 74AUP1T34GW,125 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1T34GW,125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP1T34GW,125 part is unused and in its original packaging.
Return procedure for 74AUP1T34GW,125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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