Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Logic > Buffers, Drivers, Receivers, Transceivers

Nexperia USA Inc. 74AUP1T34GW-Q100H

Name: 74AUP1T34GW-Q100H
Brand: Nexperia USA Inc.
SKU: 74AUP1T34GW-Q100H
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: 74AUP1T34GW-Q100H

Manufacturer:: Nexperia USA Inc.

Category:: Buffers, Drivers, Receivers, Transceivers

Package:: 5-TSSOP, SC-70-5, SOT-353

Datasheet:: 74AUP1T34GW-Q100H.pdf

Description:: IC TRANSLATOR UNIDIR 5TSSOP

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:1,920

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

74AUP1T34GW-Q100 from Nexperia is a single-channel, dual-supply translating buffer with independent VCC(A) and VCC(Y) rails (1.1 V to 3.6 V each), Schmitt-trigger inputs for noise immunity, IOFF partial power-down protection, and AEC-Q100 Grade 1 qualification for automotive use. It enables level translation between mismatched logic domains in body control modules and infotainment interfaces.

For engineers reviewing the 74AUP1T34GW-Q100 datasheet, 74AUP1T34GW-Q100 pinout, 74AUP1T34GW-Q100 application, or 74AUP1T34GW-Q100 equivalent, key selection criteria include dual-rail voltage flexibility, sub-1 µA static ICC, IOFF-enabled safe power sequencing, and TSSOP5 package compatibility with automated optical inspection (AOI) in automotive PCB assembly.

Technical Context

This device implements a unidirectional, non-inverting buffer with input referenced to VCC(A) and output referenced to VCC(Y), enabling true bidirectional voltage domain isolation. The Schmitt-trigger input threshold (VIH/VIL varying with VCC(A)) ensures robust operation with slow-rising signals common in sensor interfaces and legacy MCU GPIOs.

IOFF circuitry actively disables the output when either supply is near 0 V, preventing backflow current during hot-swap or partial system power-down-critical for ASIL-B compliant subsystems. Propagation delay (tpd) ranges from 1.4 ns to 33.5 ns depending on VCC(A), VCC(Y), load capacitance (5–30 pF), and temperature (−40 °C to +125 °C).

Key Specifications

Parameter	Value and Actual Design Meaning
Supply Range	VCC(A): 1.1 V–3.6 V; VCC(Y): 1.1 V–3.6 V - supports mixed-voltage interconnects (e.g., 1.2 V FPGA core to 3.3 V CAN transceiver)
Static ICC	≤ 1.4 µA at +125 °C - enables always-on wake-up circuits without battery drain penalty
IOFF Leakage	±0.75 µA max at +125 °C - guarantees <1 µA backfeed current during VCC(Y) = 0 V while VCC(A) active
Propagation Delay	1.4 ns (min, 3.3 V→3.3 V, CL = 5 pF) to 33.5 ns (max, 1.1 V→1.1 V, CL = 30 pF, +125 °C) - defines timing margin for high-speed sensor sampling paths
Input Threshold	VIH = 0.7×VCC(A) min at +125 °C - ensures reliable HIGH detection even under worst-case voltage droop and temperature
ESD Rating	HBM: >5000 V; CDM: >1000 V - meets automotive ESD immunity requirements per ISO 10605

Pinout & Package

TSSOP5 (SOT353-1) package: plastic thin shrink small outline, 5-lead, 1.25 mm body width, lead pitch 0.65 mm, suitable for reflow and AOI-compatible automotive PCBs.

Pin	Circuit Role	Design Meaning
1	VCC(A)	Input-side supply rail - powers input stage and Schmitt trigger; must be stable before signal application
2	A	Data input - accepts 0 V to 3.6 V overvoltage-tolerant signals regardless of VCC(A) state
3	GND	Common reference - shared ground return for both supply domains; critical for noise coupling control
4	Y	Data output - driven to VCC(Y) or GND; output voltage swing tracks VCC(Y), not VCC(A)
5	VCC(Y)	Output-side supply rail - sets output logic levels and drives strength; independent of VCC(A)

Key Features

Feature	Design Value
Dual independent supply rails	VCC(A) and VCC(Y) operate independently across 1.1 V–3.6 V - eliminates need for external level shifters in multi-rail ECUs
Schmitt-trigger input	Hysteresis ≥ 0.3×VCC(A) - rejects noise on long harness traces in door module or seat control wiring
IOFF partial power-down	Active output disable when VCC(Y) = 0 V - prevents back-current into powered VCC(A) domain during sleep mode transitions
AEC-Q100 Grade 1	Qualified from −40 °C to +125 °C - certified for engine bay, transmission control, and ADAS sensor interface applications
Low dynamic power	CPD = 4.6 pF at 3.3 V - limits switching power to <10 µW at 1 MHz, critical for low-power microcontroller peripherals

Applications

Body Control Module (BCM)

Infotainment Interface

Use Scenario: Translating 1.2 V I²C signals from a low-power MCU to 3.3 V display backlight driver IC.

IC Role / Device Role / Timing Role: Unidirectional level translator with Schmitt-trigger input ensuring noise immunity on long PCB traces.

Use Value: Eliminates discrete resistor-divider or dedicated level shifter IC, reducing BOM count and layout area by 40%.

Use Scenario: Isolating 1.8 V audio codec GPIOs from 2.5 V touch controller interrupt line in head unit design.

IC Role / Device Role / Timing Role: Dual-rail buffer enabling safe hot-plug detection without cross-domain leakage.

Use Value: IOFF prevents backfeed current during touch controller power cycling, avoiding MCU reset or data corruption.

ADAS Camera Sensor Interface

Electric Power Steering (EPS)

Use Scenario: Level-shifting 1.1 V MIPI D-PHY clock enable signal to 3.3 V image signal processor (ISP) power management block.

IC Role / Device Role / Timing Role: Low-propagation-delay buffer (≤2.5 ns typical at 1.2 V→3.3 V) preserving timing margins in high-speed camera sync paths.

Use Value: Meets <5 ns skew budget for synchronized frame capture across multiple camera modules.

Use Scenario: Transmitting torque sensor status flag from 1.5 V analog front-end ASIC to 5 V motor gate driver logic in EPS ECU.

IC Role / Device Role / Timing Role: Overvoltage-tolerant input (to 3.6 V) accepts direct connection to 5 V pull-up networks without clamping diodes.

Use Value: Reduces component count by removing external protection diodes, improving functional safety FIT rate.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-supply translating buffer applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74LVC1T34DRYR	Single-supply only (1.65 V–5.5 V); no independent VCC(A)/VCC(Y); lacks IOFF and AEC-Q100 qualification	Non-automotive industrial control; cannot support partial power-down or automotive temperature range	Select only for cost-sensitive consumer electronics where dual-rail isolation and automotive qualification are unnecessary
TXB0101DCKR	Auto-direction sensing; higher ICC (10 µA typical); larger X2SON6 package; AEC-Q100 Grade 2 (−40 °C to +105 °C)	Bi-directional data lines (e.g., UART, SPI); insufficient for ASIL-B systems requiring Grade 1 thermal rating	Use only when bidirectional translation is required and +125 °C operation is not mandated

Compared with SN74LVC1T34DRYR and TXB0101DCKR, the 74AUP1T34GW-Q100 uniquely delivers independent dual-rail operation, IOFF-enabled safe power sequencing, and full AEC-Q100 Grade 1 compliance-making it the sole choice for unidirectional, high-reliability automotive signal translation where thermal and safety margins are non-negotiable.

Availability

74AUP1T34GW-Q100 is available at Aetrix Electronics and suitable for automotive body control modules, ADAS camera interfaces, electric power steering ECUs, and infotainment systems requiring stable component supply across extended temperature and lifecycle demands.

Supply support for 74AUP1T34GW-Q100 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance, high-reliability components for automotive, industrial, and mobile markets.

The 74AUP1T34-Q100 belongs to Nexperia's Automotive Ultra-low-power (AUP) logic family, engineered specifically for energy-constrained, safety-critical automotive subsystems requiring robust voltage translation and guaranteed power-down behavior.

FAQ

Can 74AUP1T34GW-Q100 translate from 3.3 V input to 1.2 V output?

Yes. With VCC(A) = 3.3 V and VCC(Y) = 1.2 V, the device accepts standard 3.3 V CMOS input levels (VIH ≥ 2.0 V) and produces 1.2 V–referenced output swings. Input overvoltage tolerance up to 3.6 V ensures safe operation without external clamping, and propagation delay remains within 10.5 ns (typical) at +25 °C.

What happens to the Y output when VCC(Y) = 0 V but VCC(A) = 3.3 V?

The IOFF circuitry forces the Y output into a high-impedance state with leakage ≤ ±0.75 µA at +125 °C, preventing back-current flow into the VCC(Y) rail. This behavior is verified per JESD78 Class II Level B latch-up testing and is critical for safe power sequencing in automotive domain controllers.

Is the Schmitt-trigger input compatible with slow-rising signals from thermistors or potentiometers?

Yes. The Schmitt-trigger hysteresis (≥0.3×VCC(A)) provides noise immunity for input rise/fall times up to 200 ns/V, supporting analog sensor interface signals with RC time constants up to ~1 µs. Input leakage remains ≤ ±0.75 µA across −40 °C to +125 °C, minimizing loading error on high-impedance sensor dividers.

Does the TSSOP5 package support automated optical inspection (AOI) in automotive PCB assembly?

Yes. The SOT353-1 (TSSOP5) package features gull-wing leads with 0.65 mm pitch, defined coplanarity (≤0.1 mm), and IPC-compliant solder joint geometry. Its 1.25 mm body width and exposed pad-free construction ensure reliable AOI detection of solder bridging, lift-off, and alignment defects per IPC-A-610 Class 3 automotive standards.

74AUP1T34GW-Q100H Specifications

Product attributes: Attribute value

Manufacturer:: Nexperia USA Inc.

Series:: 74AUP

Package/Case:: 5-TSSOP, SC-70-5, SOT-353

Packaging:: Tape & Reel (TR)

Product Status:: Active

Logic Type:: Buffer, Non-Inverting

Number of Elements:: 1

Number of Bits per Element:: 1

Input Type:: -

Output Type:: Push-Pull

Current - Output High, Low:: 4mA, 4mA

Voltage - Supply:: 1.1V ~ 3.6V

Operating Temperature:: -40°C ~ 125°C (TA)

Grade:: Automotive

Qualification:: AEC-Q100

Mounting Type:: Surface Mount

Supplier Device Package:: 5-TSSOP

74AUP1T34GW-Q100H FAQ

1.How can I place an order for 74AUP1T34GW-Q100H through Aetrix?

Please submit a Request for Quotation (RFQ) for 74AUP1T34GW-Q100H on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 74AUP1T34GW-Q100H reliable?

The price and inventory of 74AUP1T34GW-Q100H are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1T34GW-Q100H is usually 5 days.

3.What payment methods are accepted for 74AUP1T34GW-Q100H?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP1T34GW-Q100H transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 74AUP1T34GW-Q100H?

74AUP1T34GW-Q100H orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 74AUP1T34GW-Q100H order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 74AUP1T34GW-Q100H?

For technical support, including 74AUP1T34GW-Q100H datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1T34GW-Q100H requirements.

6.How does Aetrix verify that 74AUP1T34GW-Q100H is sourced from the original manufacturer or authorized distributors?

All 74AUP1T34GW-Q100H products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1T34GW-Q100H meets industry standards.

7.What is the process for return or replacement of 74AUP1T34GW-Q100H?

All 74AUP1T34GW-Q100H units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1T34GW-Q100H, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74AUP1T34GW-Q100H part is unused and in its original packaging.

Return procedure for 74AUP1T34GW-Q100H:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-03 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-01 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…