NXP Semiconductors 74AUP1T58GM,115

Overview

74AUP1T58GM,115 from Nexperia is a single-supply, low-power configurable logic gate with Schmitt-trigger inputs and voltage-level translation capability. It implements AND, OR, NAND, NOR, XOR, inverter, or buffer functions via 3-bit input configuration (A/B/C), operates from 2.3 V to 3.6 V, delivers propagation delay as low as 1.3 ns at 3.6 V, and supports partial power-down via IOFF circuitry. It is used in mixed-voltage I/O interfacing between 1.8 V logic and 3.3 V systems.

For engineers reviewing the 74AUP1T58GM,115 datasheet, 74AUP1T58GM,115 pinout, 74AUP1T58GM,115 application, or 74AUP1T58GM,115 equivalent, this device serves as a space- and power-constrained configurable logic solution requiring level translation, high noise immunity, and guaranteed operation across –40 °C to +125 °C ambient temperature.

Technical Context

The 74AUP1T58GM,115 uses a CMOS-based configurable gate architecture where three inputs (A, B, C) select one of seven logic functions via truth table mapping. Its Schmitt-trigger inputs provide hysteresis (0.10–0.60 V) for noise rejection and enable reliable switching when driven by 1.8 V signals in 3.3 V domains.

IOFF circuitry actively disables outputs during power-down, limiting backflow current to ±0.75 μA at VCC = 0 V, while static supply current remains ≤3.5 μA over full temperature range. Input tolerance extends to 3.6 V regardless of VCC, supporting overvoltage-safe interfacing.

Key Specifications

Pinout & Package

XSON6 plastic extremely thin small outline package (SOT886); 6-terminal, leadless surface-mount package; body dimensions 1.0 × 1.45 × 0.5 mm; thermal pad optional; pin 1 marked by lower-left corner indicator below marking code 'a8'.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar configurable logic gate applications.

Compared with SN74LVC1G97DBVR and 74LVC1G57GW,125, the 74AUP1T58GM,115 uniquely combines sub-2 ns propagation delay, ±0.75 μA IOFF leakage, and 0.10 V minimum hysteresis in a 1.0 × 1.45 mm XSON6 package - making it optimal for miniaturized, thermally constrained, and noise-sensitive applications.

Availability

74AUP1T58GM,115 is available at Aetrix Electronics and suitable for industrial sensor interface, automotive body control, low-power wearable controllers, and IoT edge gateway designs requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74AUP1T58GM,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance logic, analog, and MOSFET solutions optimized for efficiency, reliability, and miniaturization in high-volume electronics.

The 74AUP1T58GM,115 belongs to the Advanced Ultra-low Power (AUP) logic family, designed specifically for space-constrained, battery-operated, and mixed-voltage digital systems requiring minimal static power and robust noise immunity.

FAQ

What logic functions can the 74AUP1T58GM,115 implement?

The 74AUP1T58GM,115 implements seven logic functions-AND, OR, NAND, NOR, XOR, inverter, and buffer-by applying specific HIGH/LOW states to its three inputs (A, B, C) as defined in Table 4 of the datasheet. No external programming or configuration pins are needed; function selection is purely combinatorial and static during operation.

Does the 74AUP1T58GM,115 support true bidirectional level translation?

No. The 74AUP1T58GM,115 performs unidirectional level translation only: inputs accept 1.8 V logic while operating from 2.3–3.6 V VCC, and the output swings rail-to-rail within the VCC domain. It does not translate from VCC-domain signals down to 1.8 V; output voltage is always referenced to VCC, not to a secondary supply.

How does the IOFF feature behave when VCC is disconnected?

When VCC = 0 V, the IOFF circuitry forces the Y output into a high-impedance state with leakage current limited to ±0.75 μA maximum, preventing back-current flow from other powered rails. This behavior is verified across –40 °C to +125 °C and applies regardless of input voltage (0–3.6 V), ensuring safe hot-swap and partial power-down operation.

Can the 74AUP1T58GM,115 drive a 15 pF load at 3.6 V with <5 ns propagation delay?

Yes. At VCC = 3.6 V and VI = 3.0–3.6 V, the typical propagation delay is 2.8 ns with CL = 15 pF (Table 9), and the maximum is 5.7 ns across –40 °C to +125 °C. This meets sub-5 ns timing requirements for 100 Mbps digital control links in industrial automation interfaces.