NXP Semiconductors 74AUP1T58GM,132

Overview

74AUP1T58GM,132 from Nexperia is a single-channel, low-power configurable logic gate with Schmitt-trigger inputs and voltage-level translation capability, supporting 2.3 V to 3.6 V supply operation, 1.5 μA max ICC, IOFF partial power-down protection, and configurable AND/OR/NAND/NOR/XOR/inverter/buffer functions via three input pins (A/B/C). It enables mixed-voltage interfacing in space-constrained industrial control I/O modules.

For engineers reviewing the 74AUP1T58GM,132 datasheet, 74AUP1T58GM,132 pinout, 74AUP1T58GM,132 application, or 74AUP1T58GM,132 equivalent, this device serves as a drop-in configurable logic solution for level-shifting signal conditioning in battery-powered sensor nodes, portable medical monitors, and low-power MCU peripheral interface circuits where footprint and static current are critical.

Technical Context

The 74AUP1T58GM,132 implements a 3-input programmable logic cell using CMOS architecture with Schmitt-trigger inputs (VT+ = 0.75–1.19 V, VT− = 0.46–0.85 V at VCC = 3.0–3.6 V) enabling noise-immune operation across wide input voltage ranges. Its IOFF circuit actively disables outputs during VCC = 0 V, preventing backflow current in partial power-down systems.

It supports dynamic reconfiguration of logic function via static A/B/C input states - no clock or configuration register required - and delivers propagation delays as low as 1.3 ns (VCC = 3.0–3.6 V, VI = 3.0–3.6 V, CL = 5 pF) while maintaining <10% overshoot/undershoot and <0.8 pF input capacitance.

Key Specifications

Pinout & Package

XSON6 plastic extremely thin small outline package (SOT886), 1.0 × 1.45 × 0.5 mm body, no leads, 6 terminals, wettable flank compatible, pin 1 marked by lower-left corner notch below marking code 'a8'.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar configurable logic gate applications.

Compared with SN74LVC1G97DBVR and 74LVC1G57GW,125, the 74AUP1T58GM,132 uniquely combines ultra-low ICC, guaranteed IOFF, and Schmitt-trigger inputs in XSON6 - making it the sole choice for space-constrained, battery-operated, or mixed-voltage industrial nodes demanding zero-power-state safety.

Availability

74AUP1T58GM,132 is available at Aetrix Electronics and suitable for industrial sensor interfaces, portable medical monitors, automotive body control modules, and low-power IoT gateways requiring stable component supply across extended temperature and long-lifecycle programs.

Supply support for 74AUP1T58GM,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, analog, and MOSFET solutions for industrial, automotive, and consumer markets.

The 74AUP1T58GM,132 belongs to Nexperia's Advanced Ultra-low Power (AUP) logic family, engineered specifically for energy-sensitive applications requiring sub-microamp static current, robust level translation, and compact packaging in harsh thermal environments.

FAQ

Can the 74AUP1T58GM,132 operate with a 1.8 V supply?

No. The absolute minimum VCC is 2.3 V per Table 7. Operation below 2.3 V violates recommended conditions and may cause undefined logic behavior, increased propagation delay, or failure to meet Schmitt-trigger thresholds. For 1.8 V systems, use the input as a level-translated signal while powering the device from ≥2.3 V.

What is the maximum capacitive load the Y output can drive reliably?

The Y output is characterized up to 30 pF load capacitance (Table 9), with propagation delay increasing from 1.3 ns (CL = 5 pF) to 11.9 ns (CL = 30 pF) at worst-case VCC and temperature. Driving >30 pF risks timing violations and excessive rise/fall times; add a series resistor or buffer for heavier loads.

How is the logic function selected on the 74AUP1T58GM,132?

The logic function is selected by hardwiring the A, B, and C inputs to VCC or GND before operation - no clock, programming sequence, or configuration register is involved. Table 4 defines the output Y for each of the eight possible A/B/C combinations, enabling static configuration as AND, OR, NAND, NOR, XOR, buffer, or inverter.

Does the 74AUP1T58GM,132 require external pull-up or pull-down resistors on inputs?

No. All inputs have internal Schmitt-trigger circuitry with defined VT+ and VT− thresholds and sufficient hysteresis to reject noise without external biasing. Inputs may be directly tied to VCC or GND - no external resistors are needed for function selection or noise immunity.