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Nexperia USA Inc. 74AUP1T58GN,132

Part No.:
74AUP1T58GN,132
Manufacturer:
Nexperia USA Inc.
Category:
Translators, Level Shifters
Package:
Datasheet:
Aetrix74AUP1T58GN,132.pdf
Description:
NEXPERIA 74AUP1T58GN - LOW POWE
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Inventory:105,000

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Product details

Overview

74AUP1T58GN,132 from Nexperia is a single-channel, low-power configurable logic gate with Schmitt-trigger inputs and voltage-level translation capability, supporting 2.3 V to 3.6 V supply operation, 1.5 μA max ICC, 6-pin XSON6 (SOT1115) package, and configurable AND/OR/NAND/NOR/XOR/inverter/buffer functions via three input pins. It enables mixed-voltage interfacing in space-constrained industrial sensor nodes.

For engineers reviewing the 74AUP1T58GN,132 datasheet, 74AUP1T58GN,132 pinout, 74AUP1T58GN,132 application, or 74AUP1T58GN,132 equivalent, this device serves as a flexible, ultra-low-power logic reconfiguration element for I/O bridging, signal conditioning, and level-shifting in battery-powered embedded control systems where footprint and static power are critical.

Technical Context

The 74AUP1T58GN,132 implements a 3-input configurable gate architecture where inputs A, B, and C determine logic function via truth table mapping-no external configuration register or clock required. Its Schmitt-trigger inputs provide 0.25 V–0.56 V hysteresis across 2.3–3.6 V VCC, enabling robust noise immunity in noisy environments.

IOFF circuitry ensures <±0.75 μA power-down leakage when VCC = 0 V, blocking backflow current during partial power-down. Input overvoltage tolerance up to 3.6 V allows direct connection to 3.3 V signals while operating at 2.3 V, supporting true bidirectional level translation without external components.

Key Specifications

Parameter Value and Actual Design Meaning
VCC Range 2.3 V to 3.6 V - Enables operation across common low-voltage rails including 2.5 V and 3.3 V systems.
ICC (max) 1.5 μA at 125 °C - Guarantees sub-microwatt static power for always-on monitoring circuits.
Propagation Delay 1.3 ns (typ) at VCC = 3.3 V, CL = 5 pF - Supports >200 MHz toggle rates in high-speed digital interfaces.
Hysteresis Voltage 0.15–0.56 V - Provides noise margin against EMI-induced glitches on slow-rising or noisy control lines.
IOFF Leakage ±0.75 μA at VCC = 0 V - Prevents current backfeed into powered domains during sleep mode sequencing.
Input Overvoltage 3.6 V absolute max - Allows safe interfacing with 3.3 V logic even when VCC = 2.3 V.
Operating Temp −40 °C to +125 °C - Qualified for under-hood, industrial motor control, and outdoor edge-node deployments.

Pinout & Package

XSON6 package (SOT1115): extremely thin small outline, no leads, 0.9 × 1.0 × 0.35 mm body, 6-terminal surface-mount design optimized for high-density PCB layouts and automated assembly.

Pin/Terminal Circuit Role Design Meaning
1 (B) Data input Configurable logic operand; accepts 1.8 V–3.6 V inputs regardless of VCC level.
2 (GND) Ground reference Primary return path for all internal logic and output drivers; must be low-impedance.
3 (A) Data input Configurable logic operand; Schmitt-trigger input enables clean switching on slow edges.
4 (Y) Logic output Push-pull CMOS output capable of driving 4 mA at 3.3 V; supports fan-out to multiple 74AUP inputs.
5 (VCC) Supply voltage Power rail for internal logic and output stage; IOFF activates automatically if pulled to 0 V.
6 (C) Data input Third configuration input; determines logic function per truth table (Table 4).

Key Features

Feature Design Value
Configurable logic function Single device replaces seven discrete gates (AND/OR/NAND/NOR/XOR/inverter/buffer), reducing BOM count and layout area.
Voltage-level translation Accepts 1.8 V inputs while operating at 2.3 V VCC, eliminating need for external level shifters in mixed-supply systems.
IOFF partial power-down Output disables automatically when VCC = 0 V, preventing back-current damage during hot-swap or power sequencing.
Schmitt-trigger inputs 0.25 V typical hysteresis at 3.3 V VCC rejects >100 mV noise spikes on control lines without external RC filtering.
Ultra-low ICC 1.2 μA typical supply current at 25 °C enables multi-year battery life in wireless sensor endpoints.

Applications

Industrial Sensor Interface IoT Edge Node Power Management

Use Scenario: Interfacing analog sensor outputs with slow-rising signals to a 3.3 V microcontroller ADC trigger input.

IC Role / Device Role / Timing Role: Configured as a Schmitt-trigger buffer to clean up noisy or slow analog comparator outputs before MCU sampling.

Use Value: Eliminates external RC filter and discrete buffer, saving 2.5 mm² PCB area and reducing component count by one.

Use Scenario: Enabling/disabling power to a BLE radio module based on motion-detection interrupt from an ultra-low-power accelerometer.

IC Role / Device Role / Timing Role: Configured as an inverter to invert active-low motion interrupt, then drive enable pin of load switch with rail-to-rail swing.

Use Value: Delivers 3.3 V logic swing from 1.8 V accelerometer output without level shifter, cutting system standby current by 0.8 μA.

Automated Test Equipment (ATE) Signal Conditioning Medical Wearable Button Debounce

Use Scenario: Converting TTL-level test pattern generator outputs to 2.5 V logic for FPGA-based DUT interface.

IC Role / Device Role / Timing Role: Configured as NAND gate to combine pattern strobe and enable signals before driving FPGA I/O bank.

Use Value: Ensures clean, jitter-free enable timing with <1.5 ns propagation delay variation across temperature.

Use Scenario: Debouncing mechanical push-button inputs in a clinical-grade pulse oximeter with strict EMC requirements.

IC Role / Device Role / Timing Role: Configured as XOR gate with feedback to implement hardware debounce using internal hysteresis and propagation delay.

Use Value: Achieves <5 ms bounce suppression without software polling or external capacitors, meeting IEC 60601-1 immunity thresholds.

Equivalent & Alternatives

The following parts are listed as comparable options for similar configurable logic gate applications.

Alternative Part Technical Difference Application Difference Selection Advice
SN74LVC1G97DBVR Wider VCC range (1.65–5.5 V); higher ICC (10 μA max); no IOFF; standard CMOS (not Schmitt) inputs. Lacks power-down isolation and noise immunity; requires external pull-ups for open-drain compatibility. Prefer when interfacing legacy 5 V logic or when IOFF is not required; avoid in battery-critical or noisy environments.
74LVC1G57GW,125 Same package (TSSOP6); identical configurability; lower hysteresis (0.1 V typ); no IOFF; 10 μA ICC max. Cannot safely isolate during partial power-down; less effective on slow-rising signals like thermistor comparators. Acceptable for cost-sensitive consumer designs with full-system power cycling; not recommended for industrial partial-power architectures.

Compared with SN74LVC1G97DBVR and 74LVC1G57GW,125, the 74AUP1T58GN,132 uniquely combines sub-microwatt static power, guaranteed IOFF behavior, and Schmitt-trigger noise rejection-making it the only choice for always-on, mixed-voltage, space-constrained edge sensing.

Availability

74AUP1T58GN,132 is available at Aetrix Electronics and suitable for industrial sensor interfaces, IoT edge node power management, and medical wearable button debounce requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74AUP1T58GN,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance, reliable, and scalable logic, power, and analog solutions for automotive, industrial, and consumer markets.

The 74AUP advanced ultra-low-power logic family targets battery-operated and energy-sensitive applications where nanowatt static power, small footprint, and robust signal integrity are mandatory design constraints.

FAQ

Can 74AUP1T58GN,132 operate with 1.8 V supply?

No. The 74AUP1T58GN,132 has a minimum specified VCC of 2.3 V per Table 7. While its inputs tolerate 1.8 V logic levels for level translation, the device itself requires ≥2.3 V on VCC to guarantee correct internal logic operation, output drive strength, and IOFF functionality. Operating below 2.3 V may result in undefined output states or increased ICC.

How is logic function selected on 74AUP1T58GN,132?

Function selection is determined solely by the DC voltage levels applied to pins A, B, and C (pins 3, 1, and 6). Each unique 3-bit combination maps to a specific logic function (e.g., CBA = 001 → NAND, 010 → NOR) as defined in Table 4. No clock, programming sequence, or external memory is involved-configuration is static and immediate upon power-up or input change.

Does 74AUP1T58GN,132 support hot insertion?

Yes-its IOFF circuitry actively disables the output when VCC = 0 V, preventing back-current flow from live system buses into the unpowered device. This meets JEDEC JESD78 Class II Level B latch-up immunity (>100 mA), making it suitable for hot-plug applications such as modular sensor carriers or field-replaceable I/O boards where power sequencing cannot be guaranteed.

What is the maximum capacitive load for reliable 100 MHz switching?

At VCC = 3.3 V and Tamb = 25 °C, the 74AUP1T58GN,132 maintains <6.7 ns propagation delay with CL = 30 pF (Table 9). For 100 MHz toggling (10 ns period), CL must remain ≤15 pF to ensure sufficient setup/hold margin. Layout best practices-short traces, ground plane, and minimized stubs-are essential to stay within this limit and avoid signal integrity degradation.

74AUP1T58GN,132 Specifications

Product attributes
Attribute value
Manufacturer:
Nexperia USA Inc.
Series:
*
Package/Case:
Packaging:
Bulk
Product Status:
Active
Translator Type:
-
Channel Type:
-
Number of Circuits:
-
Channels per Circuit:
-
Voltage - VCCA:
-
Voltage - VCCB:
-
Input Signal:
-
Output Signal:
-
Output Type:
-
Data Rate:
-
Operating Temperature:
-
Grade:
-
Qualification:
-
Features:
-
Mounting Type:
-
Supplier Device Package:
-

74AUP1T58GN,132 FAQ

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The price and inventory of 74AUP1T58GN,132 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1T58GN,132 is usually 5 days.

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For technical support, including 74AUP1T58GN,132 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1T58GN,132 requirements.

6.How does Aetrix verify that 74AUP1T58GN,132 is sourced from the original manufacturer or authorized distributors?

All 74AUP1T58GN,132 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1T58GN,132 meets industry standards.

7.What is the process for return or replacement of 74AUP1T58GN,132?

All 74AUP1T58GN,132 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1T58GN,132, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74AUP1T58GN,132 part is unused and in its original packaging.

Return procedure for 74AUP1T58GN,132:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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