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NXP Semiconductors 74AUP1T58GS,132
- Part No.:
- 74AUP1T58GS,132
- Manufacturer:
- NXP Semiconductors
- Category:
- Translators, Level Shifters
- Package:
- Datasheet:
-
74AUP1T58GS,132.pdf
- Description:
- NEXPERIA 74AUP1T58GS - LOW POWE
- Quantity:
- Payment:
- Shipping:
Inventory:75,000
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Product details
Overview
74AUP1T58GS,132 from Nexperia is a single-supply, low-power configurable logic gate with Schmitt-trigger inputs and voltage-level translation capability. It implements AND, OR, NAND, NOR, XOR, inverter, or buffer functions via 3-bit configuration inputs (A, B, C), operates from 2.3 V to 3.6 V, delivers propagation delays as low as 1.3 ns at 3.6 V, and supports partial power-down via IOFF circuitry for system-level power gating in battery-powered IoT sensors and portable industrial controllers.
For engineers reviewing the 74AUP1T58GS,132 datasheet, 74AUP1T58GS,132 pinout, 74AUP1T58GS,132 application, or 74AUP1T58GS,132 equivalent, key selection criteria include its 6-terminal XSON6 package (SOT1202), sub-2 μA static ICC at 25 °C, ±0.1 μA IOFF leakage, 0.25–0.56 V hysteresis (VH), and guaranteed operation across –40 °C to +125 °C ambient range.
Technical Context
This device integrates a 3-input configurable logic core with Schmitt-trigger input thresholds (VT+ = 0.75–1.19 V, VT− = 0.46–0.85 V) enabling robust noise immunity in mixed-voltage interfaces. Its level-translating capability allows 1.8 V logic inputs to drive outputs referenced to 3.3 V VCC without external biasing.
The IOFF circuit actively disables output terminals when VCC = 0 V, blocking backflow current up to ±20 mA and supporting hot-insertion and partial power-down architectures. All inputs tolerate overvoltage up to 3.6 V independent of VCC, and output drive strength is specified at ±2.3 mA (VCC = 2.3 V) and ±4.0 mA (VCC = 3.0 V).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 2.3 V to 3.6 V - Enables direct interface between 1.8 V/2.5 V logic domains and 3.3 V systems without level shifters. |
| Static Supply Current (ICC) | Max 3.5 μA at –40 °C to +125 °C - Ensures ultra-low quiescent power in always-on sensor nodes and wearables. |
| IOFF Leakage Current | ±0.75 μA at VCC = 0 V - Prevents damaging backfeed current during partial power-down in multi-rail embedded subsystems. |
| Propagation Delay (tpd) | 1.3 ns typical at VCC = 3.6 V, CL = 5 pF - Supports high-speed signal conditioning in real-time control loops and serial bus buffering. |
| Hysteresis Voltage (VH) | 0.15–0.56 V - Provides noise margins >200 mV in electrically noisy industrial environments (e.g., motor drives, PLC I/O). |
| Input Overvoltage Tolerance | 3.6 V absolute max - Allows safe connection to 3.3 V buses while powered from 2.3 V, eliminating clamping diodes. |
| Operating Temperature | –40 °C to +125 °C - Qualified for under-hood automotive modules, industrial motor controllers, and outdoor edge devices. |
Pinout & Package
XSON6 plastic extremely thin small outline package (SOT1202); 6 terminals; body dimensions 1.0 mm × 1.0 mm × 0.35 mm; no leads; wettable flank terminals for automated optical inspection.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (B) | Data input | Configurable logic operand; Schmitt-triggered for noise rejection; accepts 0–3.6 V regardless of VCC. |
| 2 (GND) | Ground reference | 0 V return path for all internal circuitry and output loads; must be low-impedance for stable hysteresis. |
| 3 (A) | Data input | Primary logic operand; used with B and C to select function per truth table; same voltage tolerance as B. |
| 4 (Y) | Output | CMOS push-pull output; drives capacitive loads ≤30 pF with <12 ns delay; IOFF active when VCC = 0 V. |
| 5 (VCC) | Supply voltage | Single power rail (2.3–3.6 V); powers internal logic and output stage; IOFF circuit monitors this node. |
| 6 (C) | Data input | Third configuration input; determines logic function with A and B; enables 7 distinct Boolean operations. |
Key Features
| Feature | Design Value |
|---|---|
| Configurable logic function | Selects AND/OR/NAND/NOR/XOR/inverter/buffer via A/B/C inputs - eliminates need for multiple fixed-function gates in space-constrained PCBs. |
| Schmitt-trigger inputs | VT+ = 0.75–1.19 V, VT− = 0.46–0.85 V - rejects EMI-induced glitches on long traces in factory automation wiring. |
| IOFF partial power-down | Blocks bidirectional current flow when VCC = 0 V - enables safe isolation of powered subsystems during firmware updates or fault recovery. |
| Overvoltage-tolerant inputs | Withstand 3.6 V regardless of VCC setting - permits direct connection to 3.3 V microcontroller GPIOs while operating at 2.3 V. |
| Ultra-low dynamic power | CPD = 4.3 pF at VCC = 3.6 V - reduces switching power to <50 nW/MHz, critical for coin-cell–powered remote sensors. |
Applications
| Industrial Sensor Interface | Portable Medical Device Logic |
|---|---|
|
Use Scenario: Signal conditioning for analog-to-digital converter (ADC) trigger lines in battery-powered pressure sensors deployed in HVAC ducts. IC Role / Device Role / Timing Role: Configured as a Schmitt-trigger buffer to debounce mechanical switch inputs and translate 1.8 V MCU wake-up signals to 3.3 V ADC enable timing. Use Value: Eliminates external RC debounce networks and discrete level shifters, reducing BOM count by two components and saving 1.2 mm² PCB area. |
Use Scenario: Glue logic between low-power BLE SoC (1.8 V I/O) and 3.3 V display driver in handheld glucose meters. IC Role / Device Role / Timing Role: Configured as a level-translating inverter to invert reset signals while maintaining timing integrity across voltage domains. Use Value: Achieves <1.5 ns pulse skew between domains, preserving setup/hold timing for display initialization sequences. |
| Automotive Body Control Module | Smart Home Hub Signal Routing |
|
Use Scenario: Interfacing 5 V legacy CAN transceiver status pins to 3.3 V microcontroller GPIOs in door module ECUs. IC Role / Device Role / Timing Role: Configured as a NOR gate to combine two fault indicators into a single interrupt line, with level translation from 5 V to 3.3 V. Use Value: Withstands 5 V input transients without damage and maintains <5 ns propagation skew across temperature extremes. |
Use Scenario: Dynamic reconfiguration of Zigbee/Thread radio enable paths based on wireless protocol selection in multi-standard home hubs. IC Role / Device Role / Timing Role: Configured as an AND gate controlled by MCU GPIOs to gate radio enable signals, with Schmitt inputs rejecting RF-coupled noise. Use Value: Reduces standby current by 2.1 μA versus discrete transistor solution, extending hub battery life by 18 months. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar configurable logic gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74LVC1G97GW,125 | Wider VCC range (1.65–5.5 V); higher ICC (max 10 μA); no IOFF; standard CMOS (not Schmitt) inputs. | Lacks level translation and power-down safety; suitable only for single-rail 3.3 V or 5 V systems with clean signal sources. | Choose when interfacing legacy 5 V logic without partial power-down requirements and where board space allows larger TSSOP6 package. |
| SN74LVC1G57DBVR | Same 1.65–5.5 V VCC; Schmitt inputs; no IOFF; higher drive (±32 mA); larger SOT-23-6 package (2.9 × 1.6 mm). | Higher output current supports driving LEDs or longer traces but increases EMI risk; lacks backfeed protection. | Prefer for high-drive applications like LED status indicators where IOFF is unnecessary and thermal margin exceeds 100 mW. |
Compared with 74LVC1G97GW,125 and SN74LVC1G57DBVR, the 74AUP1T58GS,132 uniquely combines ultra-low ICC (<3.5 μA), guaranteed IOFF, Schmitt noise immunity, and XSON6 footprint-making it the only option for space- and power-constrained partial-power-down designs requiring mixed-voltage robustness.
Availability
74AUP1T58GS,132 is available at Aetrix Electronics and suitable for industrial sensor interfaces, portable medical devices, automotive body control modules, and smart home hub signal routing requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74AUP1T58GS,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance, reliable, and efficient logic, analog, and discrete components for automotive, industrial, mobile, and computing markets.
The 74AUP (Advanced Ultra-low Power) product line targets battery-powered and thermally constrained applications where nanowatt static power, wide voltage operation, and robust noise immunity are mandatory design requirements.
FAQ
What logic functions can the 74AUP1T58GS,132 implement?
The 74AUP1T58GS,132 implements seven distinct logic functions-AND, OR, NAND, NOR, XOR, inverter, and buffer-by applying specific HIGH/LOW combinations to its three configuration inputs (A, B, C) as defined in Table 4 of the datasheet. No external components are required; function selection is purely digital and static.
Does the 74AUP1T58GS,132 support true bidirectional level translation?
No. The 74AUP1T58GS,132 supports unidirectional level translation only: inputs accept voltages up to 3.6 V regardless of VCC (enabling 1.8 V → 3.3 V translation), but the output Y is always referenced to VCC and cannot drive lower-voltage domains without external circuitry.
How does the IOFF feature behave during power sequencing?
When VCC drops below ~0.2 V, the IOFF circuit activates within 100 ns, forcing the Y output into a high-impedance state that blocks current flow in both directions-even if external voltage is applied to Y or inputs. This prevents backfeed into a powered-down domain and meets JESD78 Class II latch-up immunity.
Can the 74AUP1T58GS,132 drive a 15 pF load at 3.6 V with <5 ns propagation delay?
Yes. At VCC = 3.6 V and VI = 3.0–3.6 V, the typical propagation delay (tpd) is 1.3 ns for CL = 5 pF and 2.1 ns for CL = 15 pF (Table 9). The maximum tpd remains ≤4.4 ns under worst-case conditions (–40 °C to +125 °C), well within the 5 ns requirement.
74AUP1T58GS,132 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- *
- Package/Case:
- Packaging:
- Bulk
- Product Status:
- Active
- Translator Type:
- -
- Channel Type:
- -
- Number of Circuits:
- -
- Channels per Circuit:
- -
- Voltage - VCCA:
- -
- Voltage - VCCB:
- -
- Input Signal:
- -
- Output Signal:
- -
- Output Type:
- -
- Data Rate:
- -
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Features:
- -
- Mounting Type:
- -
- Supplier Device Package:
- -
74AUP1T58GS,132 FAQ
1.How can I place an order for 74AUP1T58GS,132 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP1T58GS,132 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP1T58GS,132 reliable?
The price and inventory of 74AUP1T58GS,132 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1T58GS,132 is usually 5 days.
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Once your 74AUP1T58GS,132 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP1T58GS,132?
For technical support, including 74AUP1T58GS,132 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1T58GS,132 requirements.
6.How does Aetrix verify that 74AUP1T58GS,132 is sourced from the original manufacturer or authorized distributors?
All 74AUP1T58GS,132 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1T58GS,132 meets industry standards.
7.What is the process for return or replacement of 74AUP1T58GS,132?
All 74AUP1T58GS,132 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1T58GS,132, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP1T58GS,132 part is unused and in its original packaging.
Return procedure for 74AUP1T58GS,132:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74AUP1T58GS,132 Tags
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74LVC1T45GW,125
Nexperia USA Inc.
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74LVCH2T45DC,125
Nexperia USA Inc.
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SN74LVC1T45DBVR
Texas Instruments
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SN74LVC1T45DRLR
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SN74LVC1T45DPKR
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SN74LVC2T45DCTR
Texas Instruments
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74LVC2T45GT,115
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SN74LVC1T45YZPR
Texas Instruments
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LSF0102DCUR
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SN74LVC1T45DCKR
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TXS0102DCTR
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