NXP Semiconductors 74AUP1T58GW,125

Overview

74AUP1T58GW,125 from Nexperia is a single-channel, low-power configurable logic gate with Schmitt-trigger inputs and voltage-level translation capability, supporting logic functions (AND, OR, NAND, NOR, XOR, inverter, buffer) via 3-bit configuration inputs A/B/C. It operates from 2.3 V to 3.6 V, delivers ≤1.5 μA max ICC, features IOFF partial power-down protection, and is rated for -40 °C to +125 °C. It enables level-shifting between 1.8 V and 3.3 V domains in portable sensor interfaces.

For engineers reviewing the 74AUP1T58GW,125 datasheet, 74AUP1T58GW,125 pinout, 74AUP1T58GW,125 application, or 74AUP1T58GW,125 equivalent, this device serves as a space-constrained, ultra-low-power logic configurator in battery-powered IoT nodes, industrial control I/O expanders, and mixed-voltage FPGA companion logic where static current, input hysteresis, and power-down isolation are critical selection criteria.

Technical Context

This device implements a single configurable gate using CMOS logic with three independent data inputs (A, B, C) that select function via truth table mapping - no external programming interface required. Its Schmitt-trigger inputs provide 0.15–0.56 V hysteresis (VH), enabling robust noise immunity in noisy industrial environments and reliable interfacing with slow-rising signals.

The IOFF circuit activates when VCC = 0 V, disabling outputs and limiting backflow current to ±0.75 μA across -40 °C to +125 °C. Input overvoltage tolerance up to 3.6 V allows safe connection to higher-voltage rails without clamping diodes, while propagation delay ranges from 1.3 ns (VCC = 3.6 V, CL = 5 pF) to 11.9 ns (VCC = 2.3 V, CL = 30 pF).

Key Specifications

Pinout & Package

TSSOP6 package (SOT363-2): plastic thin shrink small outline, 6-lead, 1.25 mm body width, 0.65 mm lead pitch, exposed pad not present.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar configurable logic gate applications.

Compared with SN74LVC1G97DBVR and 74LVC1G57GW,125, the 74AUP1T58GW,125 uniquely combines sub-μA ICC, guaranteed Schmitt thresholds below 1.2 V, and IOFF at 2.3 V minimum VCC - making it the only option for long-life, mixed-voltage, thermally demanding embedded logic.

Availability

74AUP1T58GW,125 is available at Aetrix Electronics and suitable for industrial sensor interfaces, portable medical devices, FPGA I/O expansion, and automotive body control units requiring stable component supply across extended temperature and ultra-low-power operation.

Supply support for 74AUP1T58GW,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance logic, discrete, and MOSFET solutions optimized for efficiency, reliability, and miniaturization in high-volume electronics.

The 74AUP1T58 belongs to Nexperia's Advanced Ultra-low Power (AUP) logic family, engineered specifically for battery-operated and thermally constrained applications where static power, input noise immunity, and mixed-voltage interoperability are primary design constraints.

FAQ

Can 74AUP1T58GW,125 be used to translate 1.2 V logic to 3.3 V?

No. The device's Schmitt-trigger inputs require minimum VIH of 0.60 V at VCC = 2.3 V, but its input threshold is not guaranteed below 1.65 V. Driving it with 1.2 V signals risks unreliable switching due to insufficient noise margin and undefined logic state - confirmed by Table 8 VT+ minimum of 0.60 V only at VCC ≥ 2.3 V.

Does 74AUP1T58GW,125 support true bidirectional level translation?

No. It is a unidirectional configurable gate: inputs A/B/C accept level-translated signals, and output Y drives a single logic domain referenced to VCC. There is no automatic direction sensing or dual-supply capability - the device lacks separate VCCA/VCCB rails or bus-hold circuitry required for bidirectional translation.

What is the maximum capacitive load 74AUP1T58GW,125 can drive reliably?

The datasheet specifies timing performance up to CL = 30 pF (Table 9). Driving >30 pF loads causes measurable tpd degradation (e.g., +2.2 ns delay increase at VCC = 2.3 V) and may violate setup/hold margins in high-speed interfaces. For >30 pF, add a series resistor or buffer stage to maintain signal integrity.

How does the IOFF feature behave when VCC is ramping during power-up?

IOFF activates only when VCC = 0 V. During power-up, as VCC rises from 0 V to 2.3 V, the device transitions from high-impedance (IOFF active) to functional operation - but no defined "weak pull-up/pull-down" behavior exists in the 0–2.3 V range. Output Y remains floating until VCC exceeds ~1.5 V, per typical startup characteristics in Nexperia's AUP family characterization reports.