Nexperia USA Inc. 74AUP1T86GWH

Overview

74AUP1T86GWH from Nexperia is a single 2-input EXCLUSIVE-OR gate with integrated voltage-level translation, operating from 2.3 V to 3.6 V supply while accepting 1.8 V CMOS input levels. It delivers ultra-low static current (≤1.5 μA), Schmitt-trigger inputs for noise immunity, and IOFF protection for partial power-down operation. It serves in battery-powered logic interfacing, such as I²C level-shifting between 1.8 V sensors and 3.3 V microcontrollers.

For engineers reviewing the 74AUP1T86GWH datasheet, 74AUP1T86GWH pinout, 74AUP1T86GWH application, or 74AUP1T86GWH equivalent, this device is selected for low-power dual-voltage domain XOR logic, battery voltage droop tolerance down to 2.3 V, and robust ESD performance (HBM >5000 V, CDM >1000 V) in space-constrained portable systems.

Technical Context

This device implements a single 2-input XOR function using advanced AUP (Advanced Ultra Low Power) CMOS technology. Its Schmitt-trigger inputs provide hysteresis (0.10–0.60 V) across the full temperature range (−40 °C to +125 °C), enabling reliable operation with slow-rising signals and high noise immunity.

The IOFF circuit actively disables outputs when VCC = 0 V, preventing backflow current during partial power-down-critical in mixed-supply systems. Input voltage tolerance up to 3.6 V allows safe interfacing with higher-voltage logic without external clamping.

Key Specifications

Pinout & Package

TSSOP5 (SOT353-1) package: plastic thin shrink small outline, 5-lead, 1.25 mm body width, 0.65 mm pitch, 1.3 mm height.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar XOR logic applications.

Compared with SN74LVC1G86DBVR and 74LVC1G86GW, the 74AUP1T86GWH uniquely combines ultra-low ICC, IOFF, Schmitt inputs, and high ESD robustness-making it the sole choice for battery-sensitive, noise-prone, or partial-power-down designs requiring guaranteed XOR functionality.

Availability

74AUP1T86GWH is available at Aetrix Electronics and suitable for industrial sensor interfaces, wearable health monitors, automotive body control modules, and smart home hub logic requiring stable component supply across extended temperature and low-power constraints.

Supply support for 74AUP1T86GWH includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency-enhancing components, delivering high-performance logic, analog, and MOSFET solutions for automotive, industrial, and consumer markets.

The 74AUP1T86 belongs to Nexperia's Advanced Ultra Low Power (AUP) logic family, engineered specifically for energy-constrained applications demanding robust level translation, wide supply tolerance, and fail-safe power-down behavior.

FAQ

Does 74AUP1T86GWH support true bidirectional level translation?

No. The 74AUP1T86GWH is a unidirectional XOR gate with level-translating inputs-it accepts 1.8 V inputs while powered from 2.5 V or 3.3 V, but its output swings rail-to-rail relative to VCC and cannot drive lower-voltage domains without external circuitry. It is not a bus switch or auto-direction-sensing translator.

Can 74AUP1T86GWH operate reliably at 2.3 V with 3.6 V inputs applied?

Yes. The device explicitly permits input voltages up to 3.6 V regardless of VCC (2.3–3.6 V), per Table 5 (Limiting Values) and Table 6 (Recommended Operating Conditions). This allows safe interfacing with higher-voltage logic even at minimum supply, with no risk of latch-up (JESD78 Class II compliant).

What is the functional impact of the Schmitt-trigger inputs on timing behavior?

Schmitt-trigger inputs introduce controlled hysteresis (0.10–0.56 V), which eliminates metastability and oscillation on slow or noisy edges-but they do not affect propagation delay specifications. tpd values in Table 8 are measured using standard 50 % VCC switching thresholds (VM = 0.5 × VCC), ensuring compatibility with standard timing analysis tools.

Is the IOFF feature activated automatically, or does it require external control?

IOFF activates automatically when VCC is removed or falls below ~0.2 V-no external enable/disable signal is needed. The internal circuitry detects VCC loss and disables the output driver, limiting leakage to ±0.75 μA (max) over −40 °C to +125 °C, protecting downstream circuitry during hot-swap or partial shutdown.