Nexperia USA Inc. 74AUP1T86GX,125

Overview

74AUP1T86GX,125 from Nexperia is a single 2-input EXCLUSIVE-OR gate with integrated voltage-level translation capability, operating from 2.3 V to 3.6 V supply while accepting 1.8 V CMOS input levels. It delivers ultra-low static current (≤1.5 μA), Schmitt-trigger inputs for noise immunity, and IOFF circuitry for partial power-down protection. Used in battery-powered IoT sensor interfaces requiring logic-level bridging between 1.8 V controllers and 3.3 V peripherals.

For engineers reviewing the 74AUP1T86GX,125 datasheet, 74AUP1T86GX,125 pinout, 74AUP1T86GX,125 application, or 74AUP1T86GX,125 equivalent, key selection criteria include its 2.3–3.6 V supply range, 1.5 μA max ICC, IOFF-enabled power sequencing, Schmitt-trigger hysteresis (0.15–0.56 V), and X2SON5 thermal-enhanced package for space-constrained PCBs.

Technical Context

This device implements a single 2-input XOR function with dual-voltage interface capability: inputs tolerate up to 3.6 V regardless of VCC, enabling level-shifting from 1.8 V logic domains into 2.5 V or 3.3 V systems. Its Schmitt-trigger inputs provide hysteresis (0.15–0.56 V) across the full temperature range (−40 °C to +125 °C), ensuring robust operation with slow-rising signals.

The IOFF circuit actively disables outputs when VCC = 0 V, limiting backflow current to ±0.75 μA and supporting hot-insertion and multi-rail power sequencing. Propagation delay ranges from 1.1 ns (VCC = 3.6 V, CL = 5 pF) to 11.9 ns (VCC = 2.3 V, CL = 30 pF), maintaining timing predictability across supply and load conditions.

Key Specifications

Pinout & Package

X2SON5 (SOT1226-3) package: 0.8 mm × 0.8 mm × 0.32 mm body, no leads, 5-terminal thermal-enhanced construction with exposed die pad for improved heat dissipation in high-density layouts.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar XOR gate with level translation applications.

Compared with SN74LVC1G86DBVR, 74AUP1T86GX,125 offers superior power-down safety and lower static consumption; compared with 74LVC1G86GW,125, it provides better thermal management and 15% smaller area in X2SON5, making it optimal for space- and power-constrained designs.

Availability

74AUP1T86GX,125 is available at Aetrix Electronics and suitable for IoT sensor node interface, industrial PLC input conditioning, portable medical device power sequencing, and automotive body control module subsystems requiring stable component supply across extended temperature and low-power operation.

Supply support for 74AUP1T86GX,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable logic, analog, and MOSFET solutions optimized for efficiency and miniaturization in consumer, industrial, and automotive markets.

The 74AUP (Advanced Ultra-low Power) product line targets battery-operated and thermally constrained applications where sub-microamp static current, wide supply tolerance, and robust IO behavior are mandatory design requirements.

FAQ

What is the maximum input voltage the 74AUP1T86GX,125 can accept regardless of VCC?

The device accepts input voltages from 0 V to 3.6 V on pins A and B, irrespective of the applied VCC (2.3–3.6 V). This allows direct interfacing with 1.8 V, 2.5 V, or 3.3 V logic families without external level-shifting components, as confirmed in Table 6 (Recommended Operating Conditions) and Section 1 of the datasheet.

Does the 74AUP1T86GX,125 support true bidirectional level translation?

No - it is unidirectional: inputs accept wide-voltage signals (0–3.6 V), but the output Y is referenced to VCC and swings between GND and VCC. It cannot translate from VCC domain back to a lower input domain. The device functions as a level-tolerant input buffer feeding a VCC-referenced XOR output, not a bidirectional translator like dedicated TXB or LSF devices.

How does the IOFF feature behave when VCC is ramping or partially powered?

IOFF activates when VCC drops below ~0.2 V, disabling outputs and limiting leakage to ±0.75 μA. During VCC ramp-up, outputs remain in high-impedance until VCC exceeds the minimum functional threshold (~1.5 V), preventing glitching. This behavior is verified in Table 7 (Static Characteristics) under ΔIOFF and IOFF test conditions at VCC = 0 V.

Can the 74AUP1T86GX,125 drive a 50 pF load reliably?

While not characterized beyond 30 pF in the datasheet, the device maintains VOL ≤ 0.5 V and VOH ≥ VCC − 0.11 V at 4 mA drive strength. Driving 50 pF will increase propagation delay (estimated +3–4 ns vs. 30 pF) and dynamic power, but remains functional within Absolute Maximum Ratings. For production use at 50 pF, validation under worst-case VCC (2.3 V) and temperature (+125 °C) is recommended.