NXP Semiconductors 74AUP1T97GF,132

Overview

74AUP1T97GF,132 from Nexperia is a single-channel, low-power configurable logic gate with Schmitt-trigger inputs and voltage-level translation capability, supporting 1.8 V input drive in 3.3 V systems. It implements MUX, AND, OR, NAND, NOR, inverter, or buffer functions via its 3-bit configuration (A/B/C inputs), operates from 2.3 V to 3.6 V, delivers ≤5.5 ns propagation delay at 3.0 V/CL=5 pF, and features IOFF partial power-down protection. It is used in I/O bridging between mixed-voltage domains in portable industrial controllers.

For engineers reviewing the 74AUP1T97GF,132 datasheet, 74AUP1T97GF,132 pinout, 74AUP1T97GF,132 application, or 74AUP1T97GF,132 equivalent, this device serves as a space-constrained, ultra-low-static-current (≤1.5 μA) logic reconfiguration solution for voltage-translating signal conditioning in battery-powered edge nodes, sensor interface modules, and FPGA I/O expansion circuits.

Technical Context

The 74AUP1T97GF,132 implements a single configurable gate using three data inputs (A, B, C) to select one of seven logic functions via truth table mapping - no external configuration pins or registers are required. Its Schmitt-trigger inputs provide hysteresis (0.15–0.56 V) for noise immunity across temperature (−40 °C to +125 °C) and supply (2.3–3.6 V).

IOFF circuitry actively disables outputs during power-down, limiting backflow current to ±0.75 μA when VCC = 0 V, enabling safe hot-insertion in partial-power-down systems. Input overvoltage tolerance up to 3.6 V allows direct interfacing with higher-voltage logic without external level-shifting components.

Key Specifications

Pinout & Package

XSON6 plastic extremely thin small outline package (no leads); 6 terminals; body dimensions 1.0 × 1.45 × 0.5 mm (SOT886). Pin 1 index located at lower-left corner below marking code '59'.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar configurable logic gate applications.

Compared with SN74LVC1G97DBVR and 74LVC1G98GW,125, the 74AUP1T97GF,132 offers superior static power efficiency (1.5 μA vs. 10 μA) and guaranteed Schmitt noise rejection - critical for energy-constrained or electrically harsh deployments where reliability outweighs function count.

Availability

74AUP1T97GF,132 is available at Aetrix Electronics and suitable for industrial sensor interface, portable medical device I/O, and automotive body control module applications requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74AUP1T97GF,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance logic, analog, and MOSFET solutions optimized for efficiency, reliability, and miniaturization in high-volume electronics.

The 74AUP1T97GF,132 belongs to Nexperia's Advanced Ultra-low Power (AUP) logic family, designed specifically for voltage-translation and signal conditioning in space- and power-constrained portable and industrial systems.

FAQ

What logic functions can the 74AUP1T97GF,132 implement?

The 74AUP1T97GF,132 supports seven configurable logic functions - 2-input MUX, AND, OR, NAND, NOR, inverter, and buffer - determined solely by the logic states applied to its A, B, and C inputs per Table 5 in the datasheet. No external programming or configuration registers are required; function selection is purely combinational and real-time.

Does the 74AUP1T97GF,132 require external pull-up or pull-down resistors on its inputs?

No. All inputs (A, B, C) may be directly tied to VCC or GND without external biasing. The device's Schmitt-trigger inputs have defined threshold voltages (VT+ and VT−) and hysteresis, eliminating floating-input risk and enabling robust logic-level definition even with un-driven inputs in test or debug configurations.

Can the 74AUP1T97GF,132 operate with a 1.8 V supply voltage?

No. The 74AUP1T97GF,132 has a minimum recommended VCC of 2.3 V per Table 7. However, it accepts 1.8 V input signals while powered at 2.3–3.6 V - enabling level translation from 1.8 V sources into higher-voltage domains, but not as a 1.8 V–powered device itself.

How does the IOFF feature behave during system power sequencing?

When VCC drops to 0 V, the IOFF circuit forces the Y output into a high-impedance state regardless of input states, limiting leakage current to ±0.75 μA. This prevents back-driving of powered downstream circuits and avoids bus contention - critical during staggered power-up/down in multi-rail systems like industrial HMIs or modular instrumentation racks.