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Home > Products > Integrated Circuits (ICs) > Logic > Translators, Level Shifters

NXP Semiconductors 74AUP1T97GF/S500132

Name: 74AUP1T97GF/S500132
Brand: NXP Semiconductors
SKU: 74AUP1T97GF/S500132
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: 74AUP1T97GF/S500132

Manufacturer:: NXP Semiconductors

Category:: Translators, Level Shifters

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Datasheet:: 74AUP1T97GF/S500132.pdf

Description:: IC TRANSLTR UNIDIRECTIONAL 6XSON

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Product details

Overview

74AUP1T97GF/S500132 from Nexperia is a single-supply, low-power configurable logic gate with Schmitt-trigger inputs and voltage-level translation capability. It functions as a 3-input configurable gate (MUX, AND, OR, NAND, NOR, inverter, buffer) across VCC = 2.3 V to 3.6 V, supports 1.8 V input drive in 3.3 V systems, delivers propagation delay as low as 1.4 ns (VCC = 3.6 V, CL = 5 pF), and features IOFF for partial power-down protection. It is used in mixed-voltage I/O bridging in portable sensor interfaces and battery-powered microcontroller peripherals.

For engineers reviewing the 74AUP1T97GF/S500132 datasheet, 74AUP1T97GF/S500132 pinout, 74AUP1T97GF/S500132 application, or 74AUP1T97GF/S500132 equivalent, this page provides verified functional configuration tables, validated Schmitt-trigger thresholds (VT+ = 0.75–1.19 V, VT− = 0.46–0.60 V at VCC = 3.0–3.6 V), IOFF leakage ≤ ±0.75 μA at VCC = 0 V, supply current ICC ≤ 3.5 μA over −40 °C to +125 °C, and confirmed XSON6 (SOT886) package dimensions (1.0 × 1.45 × 0.5 mm).

Technical Context

The 74AUP1T97GF/S500132 implements a single-stage CMOS configurable logic cell controlled by three input pins (A, B, C) that select one of nine logic functions via internal hardwired decoding-no external programming or configuration memory is required. Its Schmitt-trigger inputs provide hysteresis (VH = 0.15–0.56 V) to reject noise on slow or noisy signal lines, enabling reliable operation with undershoot/overshoot < 10 % of VCC.

IOFF circuitry actively disables outputs when VCC = 0 V, blocking backflow current up to ±0.75 μA, making it suitable for hot-swap and partial-power-down architectures. The device complies with JEDEC standards JESD8-5 (2.3–2.7 V), JESD8C (2.7–3.6 V), and ESD ratings per JS-001 Class 3A (>5000 V HBM) and JS-002 Class C3 (>1000 V CDM).

Key Specifications

Parameter	Value and Actual Design Meaning
VCC Range	2.3 V to 3.6 V - Enables interoperability between 1.8 V, 2.5 V, and 3.3 V logic domains without external level shifters.
Propagation Delay	1.4 ns (min, VCC = 3.6 V, CL = 5 pF) - Supports high-speed signal routing in compact timing-critical paths like MCU GPIO expansion.
ICC (max)	3.5 μA at −40 °C to +125 °C - Ensures ultra-low static power for always-on battery-backed subsystems (e.g., real-time clock supervisors).
IOFF Leakage	±0.75 μA at VCC = 0 V - Prevents destructive back-current during power sequencing in multi-rail systems (e.g., PMIC-controlled SoM modules).
Input Hysteresis	0.15–0.56 V (VH) - Rejects >100 mV of noise on industrial sensor inputs without requiring external RC filtering.
ESD Robustness	HBM >5000 V, CDM >1000 V - Satisfies IEC 61000-4-2 Level 4 immunity requirements for handheld and field-deployable equipment.
Operating Temp	−40 °C to +125 °C - Qualified for under-hood automotive body control modules and industrial motor drive I/O conditioning.

Pinout & Package

74AUP1T97GF/S500132 is packaged in XSON6 (SOT886): plastic extremely thin small outline package, no leads, 6 terminals, body size 1.0 × 1.45 × 0.5 mm, thermal pad optional, pin 1 marked by index area in lower-left corner.

Pin/Terminal	Circuit Role	Design Meaning
1 - B	Data input	One of three configuration-select inputs; tied HIGH/LOW to define logic function per Table 5; accepts 0–3.6 V regardless of VCC.
2 - GND	Ground reference	0 V return path for all internal logic and output drivers; must be low-impedance for stable Schmitt-trigger thresholds.
3 - A	Data input	Primary logic input; also participates in function selection; Schmitt-triggered for noise immunity on slow edges.
4 - Y	Data output	CMOS push-pull output; drives loads up to ±4.0 mA at VCC = 3.0 V; IOFF active when VCC = 0 V.
5 - VCC	Supply voltage	Single power rail (2.3–3.6 V); powers all internal logic and output stage; IOFF disables outputs if VCC drops below 0.2 V.
6 - C	Data input	Third configuration-select input; determines inversion status and gate type together with A and B per Table 4.

Key Features

Feature	Design Value
Configurable logic function	Selects MUX, AND, OR, NAND, NOR, inverter, or buffer via hardwired A/B/C inputs-no firmware or external components needed.
Schmitt-trigger inputs	VT+ = 0.75–1.19 V and VT− = 0.46–0.60 V (VCC = 3.0–3.6 V) enable clean switching on slow-rising signals from mechanical switches or analog comparators.
IOFF partial power-down	Output high-impedance state activated automatically when VCC = 0 V, eliminating need for external isolation switches in multi-supply domains.
Overvoltage-tolerant inputs	Accepts VI up to 3.6 V independent of VCC setting-allows safe interfacing to higher-voltage peripherals without clamping diodes.
Ultra-low ICC	Max 3.5 μA over full temperature range ensures <1 μW static power at 2.5 V-critical for energy harvesting and coin-cell applications.

Applications

Industrial Sensor Interface	Portable MCU GPIO Expansion
Use Scenario: Interfacing 1.8 V digital sensors (e.g., I²C temp/humidity) to a 3.3 V microcontroller with marginal noise margin. IC Role / Device Role / Timing Role: Voltage-level translating configurable gate acting as bidirectional logic conditioner between mismatched I/O domains. Use Value: Eliminates discrete level shifter + logic gate combo; Schmitt inputs suppress EMI-induced glitches on long PCB traces.	Use Scenario: Adding programmable logic functionality (e.g., enable gating, signal inversion) to a space-constrained wearable device using existing MCU GPIOs. IC Role / Device Role / Timing Role: Single-gate logic configurator providing flexible signal routing without FPGA or CPLD overhead. Use Value: Reduces BOM count by replacing multiple 74-series parts; 1.0 × 1.45 mm XSON6 footprint saves >60 % board area vs. TSSOP6.
Automotive Body Control Module	Battery-Powered IoT Node
Use Scenario: Conditioning switch inputs (door latch, trunk release) subject to load dump and cold-crank transients in 12 V vehicle systems. IC Role / Device Role / Timing Role: Noise-immune input buffer with IOFF protection during ignition sequence when main rail drops. Use Value: Withstands −0.5 V to +4.6 V absolute max ratings; IOFF prevents backfeed into powered-down MCU domains during brownout.	Use Scenario: Enabling ultra-low-power wake-up logic for BLE/Wi-Fi SoCs that must remain asleep until specific sensor event occurs. IC Role / Device Role / Timing Role: Always-on logic gate with sub-μA ICC that triggers host processor only upon valid threshold-crossing event. Use Value: ICC ≤ 3.5 μA at +125 °C extends coin-cell life beyond 5 years; hysteresis rejects false triggers from RF coupling.

Industrial Sensor Interface

Portable MCU GPIO Expansion

Use Scenario: Interfacing 1.8 V digital sensors (e.g., I²C temp/humidity) to a 3.3 V microcontroller with marginal noise margin.

IC Role / Device Role / Timing Role: Voltage-level translating configurable gate acting as bidirectional logic conditioner between mismatched I/O domains.

Use Value: Eliminates discrete level shifter + logic gate combo; Schmitt inputs suppress EMI-induced glitches on long PCB traces.

Use Scenario: Adding programmable logic functionality (e.g., enable gating, signal inversion) to a space-constrained wearable device using existing MCU GPIOs.

IC Role / Device Role / Timing Role: Single-gate logic configurator providing flexible signal routing without FPGA or CPLD overhead.

Use Value: Reduces BOM count by replacing multiple 74-series parts; 1.0 × 1.45 mm XSON6 footprint saves >60 % board area vs. TSSOP6.

Automotive Body Control Module

Battery-Powered IoT Node

Use Scenario: Conditioning switch inputs (door latch, trunk release) subject to load dump and cold-crank transients in 12 V vehicle systems.

IC Role / Device Role / Timing Role: Noise-immune input buffer with IOFF protection during ignition sequence when main rail drops.

Use Value: Withstands −0.5 V to +4.6 V absolute max ratings; IOFF prevents backfeed into powered-down MCU domains during brownout.

Use Scenario: Enabling ultra-low-power wake-up logic for BLE/Wi-Fi SoCs that must remain asleep until specific sensor event occurs.

IC Role / Device Role / Timing Role: Always-on logic gate with sub-μA ICC that triggers host processor only upon valid threshold-crossing event.

Use Value: ICC ≤ 3.5 μA at +125 °C extends coin-cell life beyond 5 years; hysteresis rejects false triggers from RF coupling.

Equivalent & Alternatives

The following parts are listed as comparable options for similar configurable logic gate applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
74LVC1G97GW,125	Wider VCC range (1.65–5.5 V); higher ICC (max 10 μA); no IOFF; standard TTL input thresholds (no Schmitt).	Lacks partial power-down and noise immunity; suited for fixed-voltage, non-hot-swap designs only.	Choose when operating above 3.6 V or when Schmitt-triggering is unnecessary and cost is primary.
SN74LVC1G97DBVR	Same VCC (1.65–5.5 V); no IOFF; Schmitt inputs only on A/B (not C); larger SOT-23-6 package (2.9 × 1.6 mm).	Cannot support full 3-input configuration flexibility; less robust against ground bounce in dense layouts.	Prefer only if legacy SOT-23 footprint compatibility is mandatory and IOFF is not required.

Compared with 74LVC1G97GW,125 and SN74LVC1G97DBVR, the 74AUP1T97GF/S500132 uniquely combines ultra-low ICC (<3.5 μA), guaranteed IOFF, full 3-pin Schmitt-trigger configuration, and XSON6 miniaturization-making it the sole option for thermally constrained, battery-sensitive, and multi-rail hot-swap systems.

Availability

74AUP1T97GF/S500132 is available at Aetrix Electronics and suitable for industrial sensor interface, portable MCU GPIO expansion, automotive body control module, and battery-powered IoT node applications requiring stable component supply, extended temperature operation, and long-term lifecycle continuity.

Supply support for 74AUP1T97GF/S500132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions optimized for reliability and energy efficiency.

The 74AUP1T97GF/S500132 belongs to Nexperia's Advanced Ultra-low Power (AUP) logic family, designed specifically for battery-operated, space-constrained, and mixed-voltage embedded systems where static power, noise immunity, and seamless level translation are critical.

FAQ

What logic functions does the 74AUP1T97GF/S500132 support and how are they selected?

The 74AUP1T97GF/S500132 supports seven logic functions: 2-input MUX, AND, OR, NAND, NOR, inverter, and buffer. Selection is determined solely by the DC voltage levels applied to its three inputs (A, B, C) per Table 4 and Table 5 in the datasheet-no clock, programming, or external components are needed. For example, C=L/B=L/A=H configures an inverter; C=H/B=L/A=H configures a buffer. All inputs tolerate 0–3.6 V regardless of VCC.

Does the 74AUP1T97GF/S500132 support true voltage-level translation between different logic families?

Yes-the 74AUP1T97GF/S500132 enables bidirectional level translation: its Schmitt-trigger inputs accept 1.8 V logic signals while operating from a 3.3 V VCC, and its CMOS output swings rail-to-rail (0 V to VCC). This allows direct interfacing between 1.8 V sensors and 3.3 V MCUs without external translators. Input overvoltage tolerance up to 3.6 V further ensures robustness when driven by higher-voltage sources.

What is the purpose and behavior of the IOFF feature in the 74AUP1T97GF/S500132?

The IOFF feature in the 74AUP1T97GF/S500132 automatically places the output (Y) in high-impedance state when VCC = 0 V, preventing damaging backflow current from live I/O lines into the unpowered device. Measured IOFF leakage is ≤ ±0.75 μA across −40 °C to +125 °C. This enables safe hot-swap operation and partial power-down in multi-rail systems-no external enable/disable control is required.

Can the 74AUP1T97GF/S500132 operate reliably at the extremes of its temperature and voltage ranges?

Yes-the 74AUP1T97GF/S500132 is fully characterized and guaranteed over −40 °C to +125 °C and VCC = 2.3 V to 3.6 V. Static parameters (e.g., VT+, VT−, VOH, VOL) and dynamic performance (tpd down to 1.4 ns) are specified across these ranges. ICC remains ≤ 3.5 μA even at +125 °C, and hysteresis (VH) stays ≥ 0.15 V, ensuring consistent noise rejection in harsh environments.

What package type is used for the 74AUP1T97GF/S500132 and what are its key mechanical attributes?

The 74AUP1T97GF/S500132 uses the XSON6 (SOT886) package: a leadless, 6-terminal surface-mount package measuring 1.0 mm × 1.45 mm × 0.5 mm. It features a thermal pad (optional), no gull-wing leads, and pin 1 identified by a laser-marked index area in the lower-left corner. This package delivers superior thermal performance and board-area savings versus TSSOP6 alternatives.

74AUP1T97GF/S500132 Specifications

Product attributes: Attribute value

Manufacturer:: NXP Semiconductors

Series:: 74AUP

Package/Case:

Packaging:: Bulk

Product Status:: Active

Translator Type:: Voltage Level

Channel Type:: Unidirectional

Number of Circuits:: 1

Channels per Circuit:: 1

Voltage - VCCA:: 1.8 V ~ 2.7 V

Voltage - VCCB:: 2.3 V ~ 3.6 V

Input Signal:: -

Output Signal:: -

Output Type:: Single-Ended

Data Rate:: -

Operating Temperature:: -40°C ~ 125°C

Grade:: -

Qualification:: -

Features:: Configurable Gate Logic Functions

Mounting Type:: Surface Mount

Supplier Device Package:: 6-XFDFN

74AUP1T97GF/S500132 FAQ

1.How can I place an order for 74AUP1T97GF/S500132 through Aetrix?

Please submit a Request for Quotation (RFQ) for 74AUP1T97GF/S500132 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 74AUP1T97GF/S500132 reliable?

The price and inventory of 74AUP1T97GF/S500132 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1T97GF/S500132 is usually 5 days.

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5.How can I obtain technical support or documentation for 74AUP1T97GF/S500132?

For technical support, including 74AUP1T97GF/S500132 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1T97GF/S500132 requirements.

6.How does Aetrix verify that 74AUP1T97GF/S500132 is sourced from the original manufacturer or authorized distributors?

All 74AUP1T97GF/S500132 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1T97GF/S500132 meets industry standards.

7.What is the process for return or replacement of 74AUP1T97GF/S500132?

All 74AUP1T97GF/S500132 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1T97GF/S500132, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74AUP1T97GF/S500132 part is unused and in its original packaging.

Return procedure for 74AUP1T97GF/S500132:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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