Nexperia USA Inc. 74AUP1T97GM,115

Overview

74AUP1T97GM,115 from Nexperia is a single-supply, low-power configurable logic gate with Schmitt-trigger inputs and voltage-level translation capability. It functions as a reconfigurable 3-input logic element (MUX, AND, OR, NAND, NOR, inverter, or buffer) across V_CC = 2.3 V to 3.6 V, supports partial power-down via IOFF, delivers <1.5 μA max ICC at 25 °C, and operates from –40 °C to +125 °C in XSON6 (SOT886) package. It enables level-shifting between 1.8 V logic and 3.3 V systems in space-constrained industrial sensor interfaces.

For engineers reviewing the 74AUP1T97GM,115 datasheet, 74AUP1T97GM,115 pinout, 74AUP1T97GM,115 application, or 74AUP1T97GM,115 equivalent, this device is selected for ultra-low static power, robust noise immunity in mixed-voltage I/O domains, configurable logic without external wiring, and guaranteed IOFF protection during system power sequencing.

Technical Context

The 74AUP1T97GM,115 implements a programmable logic cell using three input pins (A, B, C) to select one of seven standard Boolean functions via truth table mapping. Its Schmitt-trigger inputs provide hysteresis (V_H = 0.15–0.56 V) and overvoltage tolerance up to 3.6 V, enabling reliable interfacing with 1.8 V drivers in 3.3 V domains.

IOFF circuitry actively disables outputs when V_CC = 0 V, limiting backflow current to ±0.75 μA max across –40 °C to +125 °C. Propagation delay ranges from 1.4 ns (V_CC = 3.6 V, C_L = 5 pF) to 11.9 ns (V_CC = 2.3 V, C_L = 30 pF), with dynamic power dissipation capacitance fixed at 4.3 pF (typ.) at 3.0–3.6 V.

Key Specifications

Pinout & Package

XSON6 plastic extremely thin small outline package (SOT886); no leads; 6 terminals; body dimensions 1.0 × 1.45 × 0.5 mm; thermal pad optional; moisture sensitivity level MSL3.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar configurable logic gate applications.

Compared with 74LVC1G97GW,125 and SN74LVC1G97DBVR, the 74AUP1T97GM,115 uniquely combines sub-μA static current, guaranteed IOFF, and Schmitt-trigger noise immunity in a 1.0 × 1.45 mm XSON6 package-making it the sole option for thermally constrained, battery-sensitive, and hot-pluggable industrial applications.

Availability

74AUP1T97GM,115 is available at Aetrix Electronics and suitable for industrial sensor interfaces, automotive body control modules, portable medical monitors, and smart energy meters requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74AUP1T97GM,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions optimized for reliability and energy efficiency.

The 74AUP1T97GM,115 belongs to Nexperia's Advanced Ultra-low Power (AUP) logic family, designed specifically for space-constrained, battery-operated, and thermally demanding applications where static power, noise immunity, and mixed-voltage interoperability are critical.

FAQ

Can the 74AUP1T97GM,115 operate with V_CC = 1.8 V?

No. The device is specified only for V_CC = 2.3 V to 3.6 V per Table 7. At 1.8 V, internal logic thresholds and output drive capability fall outside guaranteed limits, and Schmitt-trigger hysteresis collapses below usable levels. Operation below 2.3 V may result in metastability or excessive propagation delay variation.

How is the logic function selected on the 74AUP1T97GM,115?

The function is determined solely by the DC voltage states applied to pins A, B, and C at power-up or during static operation, per Table 4 (Function Table) and Table 5 (Function Selection Table) in the datasheet. No clock, programming interface, or external memory is involved-configuration is purely combinatorial and immediate.

Does the 74AUP1T97GM,115 require external pull-up or pull-down resistors on inputs?

No. All inputs accept direct connection to V_CC or GND per Section 1. Inputs are internally biased and fully compatible with hard-wired logic levels. External resistors are unnecessary unless used for specific debouncing or fail-safe default states outside normal operation.

What is the maximum capacitive load the Y output can drive reliably?

The output is characterized up to C_L = 30 pF in Table 9, with t_pd values provided for 5 pF, 10 pF, 15 pF, and 30 pF loads. Driving >30 pF increases propagation delay nonlinearly and may cause overshoot/undershoot exceeding 10% of V_CC. For loads >30 pF, add series resistance or buffer stage.