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Home > Products > Integrated Circuits (ICs) > Logic > Translators, Level Shifters

Nexperia USA Inc. 74AUP1T97GM,132

Name: 74AUP1T97GM,132
Brand: Nexperia USA Inc.
SKU: 74AUP1T97GM,132
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: 74AUP1T97GM,132

Manufacturer:: Nexperia USA Inc.

Category:: Translators, Level Shifters

Package:

Datasheet:: 74AUP1T97GM,132.pdf

Description:: NEXPERIA 74AUP1T97GM - LOGIC CIR

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Inventory:100,000

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Product details

Overview

74AUP1T97GM,132 from NXP Semiconductors is a single-supply, dual-input configurable logic gate with Schmitt-trigger inputs, operating from 0.8 V to 3.6 V, delivering 3.5 ns propagation delay at 3.3 V and supporting 10 µA static current. It enables level-shifting and signal conditioning in ultra-low-power sensor interface circuits.

For engineers reviewing the 74AUP1T97GM,132 datasheet, 74AUP1T97GM,132 pinout, 74AUP1T97GM,132 application, or 74AUP1T97GM,132 equivalent, key selection criteria include input hysteresis width (±100 mV), rail-to-rail output swing, I_OFF isolation during power-down, and guaranteed operation down to 0.8 V supply.

Technical Context

This device implements a single 2-input configurable logic gate using advanced AUP (Advanced Ultra-low Power) CMOS technology. Its dual-input structure supports AND, OR, NAND, NOR, XOR, and XNOR functions via external wiring of A/B inputs and Y output - no internal configuration register or programming interface is present.

The Schmitt-trigger inputs provide noise immunity with typical hysteresis of 200 mV at V_CC = 3.3 V, and the output stage delivers full rail-to-rail swing with ±4 mA drive capability at V_CC = 3.0 V. I_OFF protection ensures signal isolation when V_CC = 0 V.

Key Specifications

Parameter	Value and Actual Design Meaning
Supply Voltage Range	0.8 V to 3.6 V - enables direct interfacing between 1.2 V, 1.8 V, 2.5 V, and 3.3 V domains without external level shifters
Propagation Delay	3.5 ns at V_CC = 3.3 V - supports timing-critical signal routing in sub-10 ns logic paths
Input Hysteresis	±100 mV typical - rejects up to 200 mV of input noise on slow or noisy signals (e.g., mechanical switch bounce)
I_OFF Current	< 0.5 µA at V_CC = 0 V - prevents back-driving of powered sections during partial power-down
Output Drive	±4 mA at V_CC = 3.0 V - sufficient to drive 15 pF load with <10 ns rise/fall times
Quiescent Current	10 µA max at V_CC = 3.3 V - suitable for battery-powered IoT endpoints with multi-year standby life

Pinout & Package

74AUP1T97GM,132 is housed in a 6-pin XSON6 (1.45 × 1.0 mm, 0.5 mm pitch) package with wettable flanks for automated optical inspection.

Pin/Terminal	Circuit Role	Design Meaning
A	Input A	Primary logic input; Schmitt-triggered, compatible with slow or noisy waveforms
B	Input B	Secondary logic input; identical electrical behavior to Pin A
Y	Output	CMOS push-pull output; rail-to-rail swing, actively driven high/low
V_CC	Supply	Single positive supply input; powers internal logic and output stage
GND	Ground	Reference return path for all I/O and internal circuitry
n.c.	No Connect	Internally unconnected pin; must be left floating or tied to GND per layout guidelines

Key Features

Feature	Design Value
Configurable Logic Function	Single gate supports AND/OR/NAND/NOR/XOR/XNOR via external wiring - no firmware or configuration overhead
Schmitt-Trigger Inputs	200 mV typical hysteresis - eliminates need for external RC filters on debounced switch or analog comparator outputs
Rail-to-Rail Output	Full V_CC–GND swing with <10 ns edge rates - ensures reliable interfacing with downstream CMOS inputs
I_OFF Protection	Sub-µA leakage when V_CC = 0 V - maintains isolation in hot-swap or multi-rail power sequencing systems

Applications

Industrial Sensor Interface

IoT Edge Node Control

Use Scenario: Interfacing mechanical limit switches and analog sensor comparators with microcontroller GPIOs in factory automation panels.

IC Role / Device Role / Timing Role: Signal conditioner and noise filter; converts slow, noisy switch transitions into clean, fast CMOS-compatible edges.

Use Value: Eliminates external RC debounce networks and reduces PCB area by >30% versus discrete resistor-capacitor solutions.

Use Scenario: Enabling wake-up logic for battery-powered environmental sensors that monitor temperature/humidity only on motion detection.

IC Role / Device Role / Timing Role: Configured as OR gate to combine PIR sensor output and timer interrupt, driving MCU reset or wake pin.

Use Value: Draws only 10 µA quiescent current while maintaining full logic functionality - extends coin-cell battery life beyond 5 years.

Low-Voltage Wearable Power Sequencing

USB-C Accessory Detection

Use Scenario: Coordinating power-up sequence of BLE SoC, display driver, and PMIC in compact wearable devices.

IC Role / Device Role / Timing Role: Level-shifting logic element translating 1.2 V enable signals to 3.3 V domain for display power control.

Use Value: Operates reliably at 0.8 V supply - supports early-stage power ramp-up before main regulator stabilizes.

Use Scenario: Detecting USB-C cable orientation and accessory presence in portable audio dongles and docking adapters.

IC Role / Device Role / Timing Role: NAND gate configured to invert CC line status, enabling host-side identification of plug insertion event.

Use Value: Schmitt-trigger inputs tolerate slow CC line ramp-up (≥100 µs), ensuring glitch-free detection without software polling.

Equivalent & Alternatives

The following parts are listed as comparable options for similar configurable logic gate applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74LVC1G97DBVR	Wider V_CC range (1.65–5.5 V); no Schmitt-trigger inputs; higher I_Q (10 µA vs. 10 µA typical but not guaranteed)	Requires external filtering for noisy inputs; unsuitable for sub-1.65 V operation	Select when system uses 5 V logic or needs higher drive strength (±32 mA)
74LVC1G57GV,125	Same AUP family; identical Schmitt inputs and 0.8–3.6 V range; slightly slower t_PD (4.1 ns)	Functionally identical but lacks n.c. pin - different package (SOT353) limits layout flexibility	Prefer for cost-sensitive designs where XSON6 footprint is not required

Compared with SN74LVC1G97DBVR and 74LVC1G57GV,125, the 74AUP1T97GM,132 uniquely combines sub-1 V operation, guaranteed Schmitt inputs, and XSON6 packaging - making it optimal for space-constrained, ultra-low-power edge nodes requiring robust noise immunity.

Availability

74AUP1T97GM,132 is available at Aetrix Electronics and suitable for industrial sensor interfaces, IoT edge node control, and low-voltage wearable power sequencing requiring stable component supply and long-term lifecycle support.

Supply support for 74AUP1T97GM,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.

The 74AUP logic family targets ultra-low-power, small-footprint digital interface and signal conditioning in battery-operated and energy-harvesting systems - emphasizing rail-to-rail operation, sub-1 V compatibility, and robust noise immunity.

FAQ

What logic functions can be implemented with the 74AUP1T97GM,132?

The 74AUP1T97GM,132 is a single 2-input configurable gate: by externally wiring inputs A and B and output Y, it implements AND, OR, NAND, NOR, XOR, or XNOR. No internal configuration is needed - function is determined solely by external connections and does not require programming or control pins.

Does the 74AUP1T97GM,132 support partial power-down operation?

Yes. The device features I_OFF circuitry that disables input/output paths when V_CC = 0 V, limiting leakage to <0.5 µA. This prevents back-current flow and signal corruption in multi-rail systems where one supply may be inactive while others remain powered.

Can the 74AUP1T97GM,132 be used for level translation between 1.2 V and 3.3 V domains?

Yes. With guaranteed operation from 0.8 V to 3.6 V and rail-to-rail CMOS output, it accepts 1.2 V inputs and drives 3.3 V logic levels directly. Input thresholds scale with V_CC, and Schmitt-trigger hysteresis remains effective across the full supply range.

Is the n.c. pin on the XSON6 package required to be grounded?

No. Pin 6 is internally unconnected. NXP's datasheet specifies it may be left floating or tied to GND for mechanical stability - neither choice affects electrical performance. Layout guidelines recommend connecting it to GND to improve solder joint reliability during reflow.

74AUP1T97GM,132 Specifications

Product attributes: Attribute value

Manufacturer:: Nexperia USA Inc.

Series:: *

Package/Case:

Packaging:: Bulk

Product Status:: Active

Translator Type:: -

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Number of Circuits:: -

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Voltage - VCCA:: -

Voltage - VCCB:: -

Input Signal:: -

Output Signal:: -

Output Type:: -

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Supplier Device Package:: -

74AUP1T97GM,132 FAQ

1.How can I place an order for 74AUP1T97GM,132 through Aetrix?

Please submit a Request for Quotation (RFQ) for 74AUP1T97GM,132 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 74AUP1T97GM,132 reliable?

The price and inventory of 74AUP1T97GM,132 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1T97GM,132 is usually 5 days.

3.What payment methods are accepted for 74AUP1T97GM,132?

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4.How is shipping managed for 74AUP1T97GM,132?

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Once your 74AUP1T97GM,132 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 74AUP1T97GM,132?

For technical support, including 74AUP1T97GM,132 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1T97GM,132 requirements.

6.How does Aetrix verify that 74AUP1T97GM,132 is sourced from the original manufacturer or authorized distributors?

All 74AUP1T97GM,132 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1T97GM,132 meets industry standards.

7.What is the process for return or replacement of 74AUP1T97GM,132?

All 74AUP1T97GM,132 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1T97GM,132, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74AUP1T97GM,132 part is unused and in its original packaging.

Return procedure for 74AUP1T97GM,132:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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